 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| t he f ol l o w i ng do c um en t c o nta i ns i nf orm ati on o n c y pr es s produc ts .
mb9a110a series 32 - bit arm ? cortex ? - m3 based microcontroller MB9AF111LA/ma/na, mb9af112la/ma/na, mb9af114la/ma/na, mb9af115ma/na, mb9af116ma/na data sheet (full production) publication number m b9a110a - ds706 - 00011 revision 3.0 issue date december 1 6 , 2014 confidential notice to readers: this document states the current technical specifications regarding the spansion product(s) described herein. spansion inc. deems the products to have been in sufficient production volume such that subsequent versions of this document ar e not expected to change. however, typographical or specification corrections, or modifications to the valid combinations offered may occur. d a t a s h e e t mb9a110a - ds706 - 00011 - 3v0 - e, december 1 6 , 2014 confidential notice on data sheet designations spansion inc. issues data sheets with advance information or preliminary designa tions to advise readers of product information or intended specifications throughout the product life cycle, including development, qualification, initial production, and full production. in all cases, however, readers are encouraged to verify that they ha ve the latest information before finalizing their design. the following descriptions of spansion data sheet designations are presented here to highlight their presence and definitions. advance information the advance information designation indicates tha t spansion inc. is developing one or more specific products, but has not committed any design to production. information presented in a document with this designation is likely to change, and in some cases, development on the product may discontinue. spans ion inc. therefore places the following conditions upon advance information content: this document contains information on one or more products under development at spansion inc. the information is intended to help you evaluate this product. do not design in this product without contacting the factory. spansion inc. reserves the right to change or discontinue work on this proposed product without notice. preliminary the preliminary designation indicates that the product development has progressed such tha t a commitment to production has taken place. this designation covers several aspects of the product life cycle, including product qualification, initial production, and the subsequent phases in the manufacturing process that occur before full production i s achieved. changes to the technical specifications presented in a preliminary document should be expected while keeping these aspects of production under consideration. spansion places the following conditions upon preliminary content: this document stat es the current technical specifications regarding the spansion product(s) described herein. the preliminary status of this document indicates that product qualification has been completed, and that initial production has begun. due to the phases of the man ufacturing process that require maintaining efficiency and quality, this document may be revised by subsequent versions or modifications due to changes in technical specifications. combination some data sheets contain a combination of products with differ ent designations (advance information, preliminary, or full production). this type of document distinguishes these products and their designations wherever necessary, typically on the first page, the ordering information page, and pages with the dc charact eristics table and the ac erase and program table (in the table notes). the disclaimer on the first page refers the reader to the notice on this page. full production (no designation on document) when a product has been in production for a period of time s uch that no changes or only nominal changes are expected, the preliminary designation is removed from the data sheet. nominal changes may include those affecting the number of ordering part numbers available, such as the addition or deletion of a speed opt ion, temperature range, package type, or vio range. changes may also include those needed to clarify a description or to correct a typographical error or incorrect specification. spansion inc. applies the following conditions to documents in this category: this document states the current technical specifications regarding the spansion product(s) described herein. spansion inc. deems the products to have been in sufficient production volume such that subsequent versions of this document are not expected to change. however, typographical or specification corrections, or modifications to the valid combinations offered may occur. questions regarding these document designations may be directed to your local sales office. mb9a110a series 32 - bit arm ? cortex ? - m3 based microcontroller MB9AF111LA/ma/na, mb9af112la/ma/na, mb9af114la/ma/na, mb9af115ma/na, mb9af116ma/na data sheet (full production) publication number mb9a110a - ds706 - 00011 revision 3.0 issue date december 1 6 , 2014 confidential this document states the current technical specifications regarding the spansion product(s) described herein. spansion inc. d eems the products to have been in sufficient production volume such that subsequent versions of this document are not expected to change. however, typographical or specif ication corrections, or modifications to the valid combinations offered may occur. ? description the mb9a110a series are a highly integrated 32 - bit microcontroller that target for high - performance and cost - sensitive embedded control applications. the mb9a110a series are based on the arm cortex - m3 processor and on - chip flash memory and sram, and peripheral functions, including motor control timers, adcs and communication interfaces (uart, c sio, i 2 c, lin). the products which are described in this data sheet are placed into type1 product categories in " fm3 family peripheral manual ". note: arm and cortex are the registered tradem arks of arm limited in the eu and other countries. d a t a s h e e t 2 mb9a110a - ds706 - 00011 - 3v0 - e, december 1 6 , 2014 confidential ? features ? 32 - bit arm cortex - m3 core ? processor version: r2p 1 ? up to 40 mhz frequency operation ? integrated nested vectored interrupt controller (nvic): 1 nmi ( non - maskable interrupt) and 48 peripheral interr upts and 16 priority levels ? 24 - bit system timer (sys tick): system timer for os task management ? on - chip memories [flash memory] ? up to 512 k byte ? read cycle: 0wait - cycle ? security function for code protection [sram] this series contain a total of up to 32 kby te on - chip sram . on - chip sram i s composed of two independent sram (sram0,sram1) . sram0 is connected to i - code bus and d - code bus of cortex - m3 core. sram1 is connected to system bus. ? sram0: up to 16 k byte s ? sram1: up to 16 k byte s ? multi - function s erial i nterface ( max 8 channels ) ? 4 channels with 16 steps 9bit fifo ( ch.4 - ch. 7), 4 channels without fifo ( ch.0 - ch. 3) ? operation mode is selectable from the followings for each channel . ? uart ? csio ? lin ? i 2 c [uart] ? full - duplex double buffer ? selection with or without parity supported ? built - in dedicated baud rate generator ? external clock available as a serial clock ? hardware flow control : automatically control the transmission by cts/rts (only ch.4) * ? various error detect ion functions available (parity errors, framing errors, and overrun errors) * : MB9AF111LA , f312l a and f314l a do not support hardware flow control [csio] ? full - duplex double buffer ? built - in dedicated baud rate generator ? overrun error detect ion function available [lin] ? lin protocol rev. 2.1 suppor ted ? full - duplex double buffer ? master/slave mode supported ? lin break field generation (can be changed 13 - 16bit length) ? lin break delimiter generation (can be changed 1 - 4bit length) ? various error detect ion functions available (parity errors, framing errors, and overrun errors) [i 2 c] standard - mode (max 100kbps) / fast - mode (max 400kbps) supported d a t a s h e e t december 1 6 , 2014 , mb9a110a - ds706 - 0 0011 - 3v0 - e 3 confidential ? external bus interface * ? supports sram, nor flash device ? up to 8 chip selects ? 8/16 - bit data width ? up to 25 - bit address bit ? maximum area size : up to 256 mbytes ? supports address/data multiplex ? supports external rdy function * : MB9AF111LA , f312l a and f314l a do not support external bus interface ? dma controller (8channels) the dma controller has an independent bus from the cpu, so cpu and dma controller can process simultaneously . ? 8 independently configured and operated channels ? transfer can be started by software or request from the built - in peripherals ? transfer address area: 32bit(4gbyte s ) ? transfer mode: block transfer/burst transfer/demand transfer ? transfe r data type: byte/half - word/word ? transfer block count: 1 to 16 ? number of transfers: 1 to 65536 ? a/d converter ( max 16channels) [ 12 - bit a/d converter ] ? successive approximation type ? built - in 3unit s * ? conversion time: 1.0 s@5v ? priority conversion available (priority at 2levels) ? scanning conversion mode ? built - in fifo f or conversion data storage ( for scan conversion: 16steps, for priority conversion: 4steps) * : MB9AF111LA, f112la , f114la built - in 2unit s ? base timer ( max 8c hannels) operation mode is selectable from the followings for each channel. ? 16 - bit pwm timer ? 16 - bit ppg timer ? 16/32 - bit reload timer ? 16/32 - bit pwc timer d a t a s h e e t 4 mb9a110a - ds706 - 00011 - 3v0 - e, december 1 6 , 2014 confidential ? multi - function t imer ( max 2 unit s ) the multi - function timer is composed of the following blocks. ? 16 - bi t free - run timer 3ch/unit ? input capture 4ch/unit ? output compare 6ch/unit ? a/d activati on compare 3ch/unit ? waveform generator 3 ch/unit ? 16 - bit ppg timer 3ch/unit the following function can be used to achieve the motor control. ? pwm signal output f unction ? dc chopper waveform output function ? dead time r function ? input capture function ? a/d convert e r activate function ? dtif ( motor emergency stop) interrupt function ? quadrature position /revolution counter (qprc) ( max 2unit s ) the quadrature position/revolu tion counter (qprc) is used to measure the position of the position encoder. moreover, it is possible to use up/down counter. ? the detection edge of the three external event input pins ain, bin and zin is c o nfigurable. ? 16 - bit position counter ? 16 - bit revolut ion counter ? two 16 - bit compare registers ? dual timer (32/16bit down counter) the dual timer consists of two programmable 32/16 - bit down counters. operation mode is selectable from the followings for each timer channel. ? free - running ? periodic (=reload) ? one - s hot ? watch counter the watch counter is used for wake up from low - power consumption mode. ? interval timer: up to 64s( max ) @ sub clock : 32.768khz ? watch dog t imer (2channels) a watchdog timer can generate interrupts or a reset when a time - out value is reache d. this series consists of two different watchdogs, a "hardware " watchdog and a , "software" watchdog. the "hardware" watchdog timer is clocked by the built - in low speed cr oscillator. therefore, the "hardware" watchdog is active in any low - power consumptio n modes except stop mode . d a t a s h e e t december 1 6 , 2014 , mb9a110a - ds706 - 0 0011 - 3v0 - e 5 confidential ? external interrupt controller unit ? up to 16 external interrupt input pins. ? include one non - maskable interrupt (nmi) input pin. ? general - purpose i/o port this series can use its pins as general - purpose i/o ports when they are not used for external bus or peripherals. moreover, the port relocate function is built in. it can set which i/o port the peripheral function can be allocated to. ? capable of pull - up control per pin ? capable of reading pin level directly ? b uilt - in the port reloc ate function ? up to 83 fast general purpose i / o ports @ 100 pin package ? some ports are 5v tolerant i/o ( mb9af115ma/na, mb9af116ma/na only) please see " ? pin description" to confirm the corresponding pins. ? crc (cyclic redundancy check) accelerator the crc accelerator calculates the crc which has a heavy software processing load, and achieves a reduction of the integrity check processing load for reception data and storage. ccitt crc16 and ieee - 802.3 crc32 are supported. ? ccitt crc16 generator polynomial: 0x1021 ? ieee - 802.3 crc32 generator polynomial: 0x04c11db7 ? clock and reset [clocks] selectable from five clock sources (2 external oscillators, 2 built - in cr oscillators, and main pll). ? main clock : 4 mhz to 48mhz ? sub clock : 32.768khz ? built - in high - speed cr clock : 4mhz ? built - in low - speed cr clock : 100khz ? main pll clock [resets] ? reset requests from initx p ins ? power - on reset ? software reset ? watchdog timers reset ? low - voltage detector reset ? clock supervisor reset ? clock super visor (csv) clocks generated by built - in cr oscillators are used to supervise abnormality of the external clocks. ? external clock failure ( clock stop) is detected, reset is asserted. ? external frequency anomaly is detect ed, interrupt or reset is asserted. d a t a s h e e t 6 mb9a110a - ds706 - 00011 - 3v0 - e, december 1 6 , 2014 confidential ? low - voltage detector (lvd) this series incl ude 2 - stage monitoring of voltage on the vcc. when the voltage falls below the voltage that has been set, low - voltage detector generates an interrupt or reset. ? lvd1: error reporting via interrupt ? lvd2: auto - reset operation ? low - power consumption m ode three low - power consumption modes supported. ? sleep ? timer ? stop ? debug ? serial wire jtag debug port (swj - dp) ? embedded trace macrocells (etm). * * : MB9AF111LA /m a , f312l a /m a , f314l a /m a , f315m a and f316m a support only swj - dp. ? power supply ? vcc = 2.7v to 5.5v: cor r esp ond to the wide range voltage. d a t a s h e e t december 1 6 , 2014 , mb9a110a - ds706 - 0 0011 - 3v0 - e 7 confidential ? product lineup ? memory size product name MB9AF111LA/ma/na mb9af112la/ma/na mb9af114la/ma/na on - chip flash memory 64kbyte s 128kbyte s 256kbyte s on - chip sram 16kbyte s 16kbyte s 32kbyte s product name mb9af115ma/na mb9af116ma/n a on - chip flash memory 384kbyte s 512kbyte s on - chip sram 32kbyte s 32kbyte s ? function product name MB9AF111LA mb9af112la mb9af114la mb9af111ma mb9af112ma mb9af114ma mb9af115ma mb9af116ma mb9af111na mb9af112na mb9af114na mb9af115na mb9af116na pin count 64 80 100 cpu cortex - m3 freq. 40mhz power supply voltage range 2.7v to 5.5v dmac 8ch . external bus interface - addr:2 1 - bit ( max ) data:8 - bit cs: 4 ( max ) support : sram , nor flash addr:25 - bit ( max ) data:8/16 - bit cs: 8 ( max ) support : sram , nor flash multi - function serial interface (uart/csio/lin/i 2 c) 8ch . ( max ) ch.4 to ch.7: fifo (16steps 9 - bit) ch.0 to ch.3: no fifo base timer (pwc/ reload timer/pwm/ppg) 8ch . ( max ) mf - timer a/d activation compare 3ch . 1 unit 2 units ( max ) input capture 4ch . free - run timer 3ch . output compare 6ch . waveform generator 3ch . ppg 3ch . qprc 2ch . ( max ) dual timer 1 unit watch counter 1 unit crc accelerator yes watchdog timer 1ch . (sw) + 1ch . (hw) external interrupts 8 pins ( max )+ nmi 1 11pins ( max )+ nmi 1 16pins ( max )+ nmi 1 i/o ports 51pins ( max ) 66pins ( max ) 83pins ( max ) 12 - bit a/d converter 9ch . (2 units) 12ch . (3 units) 16ch . (3 units) csv (clock super visor) yes lvd (low - voltage detector) 2ch . built - in high - speed 4mhz d a t a s h e e t 8 mb9a110a - ds706 - 00011 - 3v0 - e, december 1 6 , 2014 confidential product name MB9AF111LA mb9af112la mb9af114la mb9af111ma mb9af112ma mb9af114ma mb9af115ma mb9af116ma mb9af111na mb9af112na mb9af114na mb9af115na mb9af116na cr low - sp eed 100khz debug function swj - dp swj - dp/etm note: all signals of the peripheral function in each product cannot be allocated by limiting the pins of package. it is necessary to use the port relocate function of the i/o port according to your functi on use. see " ? electrical characteristics 4.ac characteristics (3)built - in cr oscillation characteristics" for accuracy of built - in cr . d a t a s h e e t december 1 6 , 2014 , mb9a110a - ds706 - 0 0011 - 3v0 - e 9 confidential ? packages product name package MB9AF111LA mb9af112la mb9af114la mb9af111ma mb9af112ma mb9af114ma mb9af115ma mb9af116ma mb9af111na mb 9af112na mb9af114na mb9af115na mb9af116na lqfp: fpt - 64p - m38 (0.5mm pitch) ? ? - - lqfp: fpt - 64p - m39 (0.65mm pitch) ? ? - - qfn: lcc - 64p - m24 (0.5mm pitch) ? ? - - lqfp: fpt - 80p - m 37 (0.5mm pitch) - ? ? - lqfp: fpt - 100p - m23 (0.5mm pitch) - - ? ? q fp: fpt - 100p - m06 (0.65mm pitch) - - ? ? bga: bga - 112p - m04 (0.8mm pitch) - - ? * ? : supported * : mb9af115na, mb9af116na are planning note: refer to " ? package dimensions" for detailed information on each package. d a t a s h e e t 10 mb9a110a - ds706 - 00011 - 3v0 - e, december 1 6 , 2014 confidential ? pin assignment ? fpt - 100p - m23 (top view) d a t a s h e e t december 1 6 , 2014 , mb9a110a - ds706 - 00011 - 3v0 - e 11 confidential ? fpt - 10 0p - m 06 (top view) d a t a s h e e t 12 mb9a110a - ds706 - 00011 - 3v0 - e, december 1 6 , 2014 confidential ? fpt - 80p - m37 (top view) d a t a s h e e t december 1 6 , 2014 , mb9a110a - ds706 - 00011 - 3v0 - e 13 confidential ? fpt - 64p - m38/m39 (top view) d a t a s h e e t 14 mb9a110a - ds706 - 00011 - 3v0 - e, december 1 6 , 2014 confidential ? bga - 112p - m04 d a t a s h e e t december 1 6 , 2014 , mb9a110a - ds706 - 00011 - 3v0 - e 15 confidential ? lcc - 64p - m24 (top view) d a t a s h e e t 16 mb9a110a - ds706 - 00011 - 3v0 - e, december 1 6 , 2014 confidential ? list of pin functions ? list of pin numbers the number after the underscore ( " _ " ) in pin names such as xxx_1 and xxx_2 indicates the relocate d port number. for these pins, there are multiple pins that provide the same function for the same channel. use the extended port function register (epfr) to select the pin pin no pin name i/o circuit type pin state type lqfp - 100 qfp - 100 bga - 112 lqfp - 80 l qfp - 64 qfn - 64 1 79 b1 1 1 vcc - 2 80 c1 2 2 p50 e h int00_0 ain0_2 sin3_1 - rto10_0 (ppg10_0) m a data 00_1 3 81 c2 3 3 p51 e h int01_0 bin0_2 sot3_1 (sda3_1) - rto11_0 (ppg10_0) m a data 0 1 _1 4 82 b3 4 4 p52 e h int02_0 zin0_2 sck3_1 (scl3_1) - rto12_0 (ppg12_0) m a data 0 2 _1 5 83 d1 5 - p53 e h sin6_0 tioa1_2 int07_2 rto13_0 (ppg12_0) m a data 0 3 _1 6 84 d2 6 - p54 e i sot6_0 (sda6_0) tiob1_2 rto14_0 (ppg14_0) m a data 0 4 _1 d a t a s h e e t december 1 6 , 2014 , mb9a110a - ds706 - 00011 - 3v0 - e 17 confidential pin no pin name i/o circuit type pin state type lqfp - 100 qfp - 100 bga - 112 lqfp - 80 l qfp - 64 qfn - 64 7 85 d3 7 - p55 e i sck6_0 (scl6_0) a dtg _ 1 rto15_0 (ppg14_0) m a data 0 5 _1 8 86 d5 8 - p56 e h int08_2 dtti1x_0 m adata06_1 9 87 e1 9 5 p30 e h ain0_0 tiob0_1 int03_2 - madata0 7 _ 1 10 88 e2 10 6 p31 e h bin0_0 tiob1_1 sck6_1 (scl6_1) int04_2 - madata0 8 _ 1 11 89 e3 11 7 p32 e h zin0_0 tiob2_1 sot6_1 (sda6_1) int05_2 - madata09_1 12 90 e4 12 8 p33 e h int04_0 tiob3_1 sin6_1 adtg_6 - madata10_1 13 91 f1 - - p34 e i frck0_0 tiob4_1 madata11_1 d a t a s h e e t 18 mb9a110a - ds706 - 00011 - 3v0 - e, december 1 6 , 2014 confidential pin no pin name i/o circuit type pin state type lqfp - 100 qfp - 100 bga - 112 lqfp - 80 l qfp - 64 qfn - 64 14 92 f2 - - p35 e h ic03_0 t iob5_1 int08_1 mad ata12_1 15 93 f3 - - p36 e h ic02_0 sin5_2 int09_1 madata13_1 16 94 g1 - - p37 e h ic01_0 sot5_2 (sda5_2) int10_1 m adata14_1 17 95 g2 - - p38 e h i c00_0 sck5_2 (scl5_2) int11_1 madata15_1 18 96 f4 13 9 p39 e i dtti0x_0 adtg_2 19 97 g3 14 10 p3a g i rto00_0 (ppg00_0) tioa0_1 20 98 h1 15 11 p3b g i rto01_0 (ppg00_0) tioa1_1 2 1 99 h2 16 12 p3c g i rto02_0 (ppg02_0) tioa2_1 22 100 g4 17 13 p3d g i rto03_0 (ppg02_0) tioa3_1 - - b2 - - vss - d a t a s h e e t december 1 6 , 2014 , mb9a110a - ds706 - 00011 - 3v0 - e 19 confidential pin no pin name i/o circuit type pin state type lqfp - 100 qfp - 100 bga - 112 lqfp - 80 l qfp - 64 qfn - 64 23 1 h3 18 14 p3e g i rto04_0 (ppg04_0) tioa4_1 24 2 j2 19 15 p3f g i rto05_0 (ppg04_0) tioa5_1 25 3 l1 20 16 vss - 26 4 j1 - - vcc - 27 5 j4 - - p40 g h tioa0_0 rto10_1 (ppg10_1) int12_1 28 6 l5 - - p41 g h tioa1_0 rto11_1 (ppg10_1) int13_1 29 7 k5 - - p42 g i tioa2_0 rto12_1 (ppg12_1) 30 8 j5 - - p43 g i tioa3_0 rto13_1 (ppg12_1) adtg_7 31 9 h5 21 - p44 g i tioa4_0 ma d00_1 - rto14_1 (ppg14_1) 32 10 l6 22 - p45 g i tioa5_0 mad01_1 - rto15_1 (ppg14_1) - - k2 - - vss - - - j3 - - vss - - - h4 - - vss - d a t a s h e e t 20 mb9a110a - ds706 - 00011 - 3v0 - e, december 1 6 , 2014 confidential pin no pin name i/o circuit type pin state type lqfp - 100 qfp - 100 bga - 112 lqfp - 80 l qfp - 64 qfn - 64 33 11 l2 23 17 c - 34 12 l4 24 - vss - 35 13 k1 25 18 vcc - 36 14 l3 26 19 p46 d m x0a 37 15 k3 27 20 p47 d n x1a 38 16 k4 28 21 initx b c 39 17 k6 29 - p48 e h dtti1x_1 int14_1 sin3_2 mad02_1 40 18 j6 30 22 p49 e i tiob0_0 ain0_1 - ic10_1 sot3_2 (sda3_2) mad03_1 41 19 l7 31 23 p4a e i tiob1_0 bin0_1 - ic11_1 sck3_2 (scl3_2) mad04_1 42 20 k7 32 24 p4b e i tiob2_0 zin0_1 - ic12_1 mad05_1 43 21 h6 33 25 p4c e / i* i tiob3_0 sck7_1 (scl7_1) ain1_2 - ic13_1 mad06_1 d a t a s h e e t december 1 6 , 2014 , mb9a110a - ds706 - 00011 - 3v0 - e 21 confidential pin no pin name i/o circuit type pin state type lqfp - 100 qfp - 100 bga - 11 2 lqfp - 80 l qfp - 64 qfn - 64 44 22 j7 34 26 p4d e / i * i tiob4_0 sot7_1 (sda7_1) bin1_2 - frck1_1 mad07_1 45 23 k8 35 27 p4e e / i * i tiob5_0 int06_2 sin7_1 zin1_2 - mad08_1 46 24 k9 36 28 md1 c p pe0 47 25 l8 37 29 md0 j d 48 26 l9 38 30 x0 a a pe2 49 27 l10 39 31 x1 a b pe3 50 28 l11 40 32 vss - 51 29 k11 41 33 vcc - 52 30 j11 42 34 p10 f k an00 53 31 j10 43 35 p11 f l an01 sin1_1 int02_1 frck0_2 - mad09_1 54 32 j8 44 36 p12 f k an02 sot1_1 (sda1_1) ic00_2 - mad10_1 - - k10 - - vss - - - j9 - - vss - d a t a s h e e t 22 mb9a110a - ds706 - 00011 - 3v0 - e, december 1 6 , 2014 confidential pin no pin name i/o circuit type pin state type lqfp - 100 qfp - 10 0 bga - 112 lqfp - 80 l qfp - 64 qfn - 64 55 33 h10 45 37 p13 f k an03 sck1_1 (scl1_1) ic01_2 - mad11_1 56 34 h9 46 38 p14 f l an04 int03_1 ic02_2 - sin0_1 mad12_1 57 35 h7 47 39 p15 f k an05 ic03_2 - sot0_1 (sda0_1) mad13_1 58 36 g10 48 - p16 f k an06 sck0_1 (scl0_1) mad14_1 59 37 g9 49 40 p17 f l an07 sin2_2 int04_1 - mad15_1 60 38 h11 50 41 avcc - 61 39 f11 51 42 avrh - 62 40 g11 52 43 avss - 63 41 g8 53 44 p18 f k an08 sot2_2 (sda2_2) - mad16_1 64 42 f10 54 45 p19 f k an09 sck2_2 (scl2_2) - mad17_1 - - h8 - - vss - d a t a s h e e t december 1 6 , 2014 , mb9a110a - ds706 - 00011 - 3v0 - e 23 confidential pin no pin name i/o circuit type pin state type lqfp - 100 qfp - 100 bga - 112 lqfp - 80 l qfp - 64 qfn - 64 65 43 f9 55 - p1a f l an10 sin4_1 int05_1 ic00_1 mad18_1 66 44 e11 56 - p1b f k an11 sot4_1 (sda4_1) ic01_1 mad19_1 67 45 e10 - - p1c f k an12 sck4_1 (scl4_1) ic02_1 mad20_1 68 46 f8 - - p1d f k an13 cts4_1 ic03_1 mad21_1 69 47 e9 - - p1e f k an14 rts4_1 dtti0x_1 mad22_1 70 48 d11 - - p1f f k an15 adtg_5 frck0_1 mad23_1 - - b10 - - vss - - - c9 - - vss - d a t a s h e e t 24 mb9a110a - ds706 - 00011 - 3v0 - e, december 1 6 , 2014 confidential pin no pin name i/o circuit type pin state type lqfp - 100 qfp - 100 bga - 112 lqfp - 80 l qfp - 64 qfn - 64 7 1 49 d10 57 46 p23 e i sck0_0 (scl0_0) tioa7_1 - - rto00_1 (ppg00_1) 7 2 50 e8 58 47 p22 e i sot0_0 (sda0_0) tiob7_1 - zin1_1 7 3 51 c11 59 48 p21 e h sin0_0 int06_1 - bin1_1 7 4 52 c10 60 - p20 e h int05_0 crout _0 ain1_1 mad24_1 75 53 a11 - - vss - 76 54 a10 - - vcc - 77 55 a9 61 49 p00 e e trstx - mcsx7_1 78 56 b9 62 50 p01 e e tck swclk 79 57 b11 63 51 p02 e e tdi - mcsx6_1 80 58 a8 64 52 p03 e e tms swdio 81 59 b8 65 53 p04 e e tdo swo 82 60 c8 - - p05 e f traced0 tioa5_2 sin4_2 int00_1 mcsx5_1 - - d8 - - vss - d a t a s h e e t december 1 6 , 2014 , mb9a110a - ds706 - 00011 - 3v0 - e 25 confidential pin no pin name i/o circuit type pin state typ e lqfp - 100 qfp - 100 bga - 112 lqfp - 80 l qfp - 64 qfn - 64 83 61 d9 - - p06 e f traced1 tiob5_2 sot4_2 (sda4_2) int01_1 mcsx4_1 84 62 a7 66 - p07 e g adtg_0 mclkout_1 - traced2 sck4_2 (scl4_ 2) 85 63 b7 - - p08 e g traced3 tioa0_2 cts4_2 mcsx3_1 86 64 c7 - - p09 e g traceclk tiob0_2 rts4_2 mcsx2_1 87 65 d7 67 54 p0a e / i * h sin4_0 int00_2 - frck1_0 m csx1_1 88 66 a6 68 55 p0b e / i * i sot4_0 (sda4_0) tiob6_1 - ic10_0 m csx0_1 89 67 b6 69 56 p0c e / i * i sck4_0 (scl4_0) tioa6_1 - ic11_0 ma le_1 - - d4 - - vss - - - c3 - - vss - d a t a s h e e t 26 mb9a110a - ds706 - 00011 - 3v0 - e, december 1 6 , 2014 confidential pi n no pin name i/o circuit type pin state type lqfp - 100 qfp - 100 bga - 112 lqfp - 80 l qfp - 64 qfn - 64 90 68 c6 70 - p0d e i rts4_0 tioa3_2 ic12_0 mdqm0_1 91 69 a5 71 - p0e e i cts4_0 tiob3_2 ic13_0 mdqm1_1 92 70 b5 72 57 p0f e j nmix crout_1 93 71 d6 73 - p63 e h int03_0 mwex_1 94 72 c5 74 58 p62 e i sck5_0 (scl5_0) adtg_3 - moex_1 95 73 b4 75 59 p61 e i sot5_0 (sda5_0) tiob 2_2 96 74 c4 76 60 p60 e / i * h sin5_0 tioa2_2 int15_1 - mrdy_1 97 75 a4 77 61 vcc - 98 76 a3 78 62 p80 h o 99 77 a2 79 63 p81 h o 100 78 a1 80 64 vss - * : 5v tolerant i / o on mb9af115m a /n a and mb9af116m a /n a d a t a s h e e t december 1 6 , 2014 , mb9a110a - ds706 - 00011 - 3v0 - e 27 confidential ? list of pin functions the number after the underscore ( " _ " ) in pin names such as xxx_1 and xxx_2 indicates the relocated port number. for these pins, there are multiple pins that provide the same function for the same channel. use the extended p ort function register (epfr) to select the pin. module pin name function pin no lqfp - 100 qfp - 100 bga - 1 12 lqfp - 80 lq fp - 64 qfn - 64 adc adtg_0 a/d converter external trigger input pin 84 62 a7 66 - adtg_1 7 85 d3 7 - adtg_2 18 96 f4 13 9 adt g_3 94 72 c5 74 58 adtg_4 - - - - - adtg_5 70 48 d11 - - adtg_6 12 90 e4 12 8 adtg_7 30 8 j5 - - adtg_8 - - - - - an00 a/d converter analog input pin . anxx describes adc ch.xx. 52 30 j11 42 34 an01 53 31 j10 43 35 an02 54 32 j8 44 3 6 an03 55 33 h10 45 37 an04 56 34 h9 46 38 an05 57 35 h7 47 39 an06 58 36 g10 48 - an07 59 37 g9 49 40 an08 63 41 g8 53 44 an09 64 42 f10 54 45 an10 65 43 f9 55 - an11 66 44 e11 56 - an12 67 45 e10 - - an13 68 46 f8 - - a n14 69 47 e9 - - an15 70 48 d11 - - base timer 0 tioa0_0 base timer ch.0 tioa pin 27 5 j4 - - tioa0_1 19 97 g3 14 10 tioa0_2 85 63 b7 - - tiob0_0 base timer ch.0 tiob pin 40 18 j6 30 22 tiob0_1 9 87 e1 9 5 tiob0_2 86 64 c7 - - base time r 1 tioa1_0 base timer ch.1 tioa pin 28 6 l5 - - tioa1_1 20 98 h1 15 11 tioa1_2 5 83 d1 5 - tiob1_0 base timer ch.1 tiob pin 41 19 l7 31 23 tiob1_1 10 88 e2 10 6 tiob1_2 6 84 d2 6 - d a t a s h e e t 28 mb9a110a - ds706 - 00011 - 3v0 - e, december 1 6 , 2014 confidential module pin name function pin no lqfp - 100 qfp - 100 b ga - 1 12 lqfp - 80 lq fp - 64 qfn - 64 base timer 2 tioa2_0 base timer ch.2 tioa pin 29 7 k5 - - tioa2_1 21 99 h2 16 12 tioa2_2 96 74 c4 76 60 tiob2_0 base timer ch.2 tiob pin 42 20 k7 32 24 tiob2_1 11 89 e3 11 7 tiob2_2 95 73 b4 75 59 base time r 3 tioa3_0 base timer ch.3 tioa pin 30 8 j5 - - tioa3_1 22 100 g4 17 13 tioa3_2 90 68 c6 70 - tiob3_0 base timer ch.3 tiob pin 43 21 h6 33 25 tiob3_1 12 90 e4 12 8 tiob3_2 91 69 a5 71 - base timer 4 tioa4_0 base timer ch.4 tioa pin 31 9 h5 21 - tioa4_1 23 1 h3 18 14 tioa4_2 - - - - - tiob4_0 base timer ch.4 tiob pin 44 22 j7 34 26 tiob4_1 13 91 f1 - - tiob4_2 - - - - - base timer 5 tioa5_0 base timer ch.5 tioa pin 32 10 l6 22 - tioa5_1 24 2 j2 19 15 tioa5_2 82 60 c8 - - tiob5_0 base timer ch.5 tiob pin 45 23 k8 35 27 tiob5_1 14 92 f2 - - tiob5_2 83 61 d9 - - base timer 6 tioa6_1 base timer ch.6 tioa pi n 89 67 b6 69 56 tiob6_1 base timer ch.6 tiob pin 88 66 a6 68 55 base timer 7 tioa7_0 base timer ch.7 tioa pin - - - - - tioa7_1 71 49 d10 57 46 tioa7_2 - - - - - tiob7_0 base timer ch.7 tiob pin - - - - - tiob7_1 72 50 e8 58 47 tiob7_2 - - - - - d a t a s h e e t december 1 6 , 2014 , mb9a110a - ds706 - 00011 - 3v0 - e 29 confidential module pin name function pin no lqfp - 100 qfp - 100 bga - 1 12 lqfp - 80 lq fp - 64 qfn - 64 debugger s wclk serial wire debug interface clock input 78 56 b9 62 50 swdio serial wire debug interface data input / output 80 58 a8 64 52 swo serial wire viewer output 81 59 b8 65 53 tck j - tag test clock input 78 56 b9 62 50 tdi j - tag test data input 79 57 b11 63 51 tdo j - tag debug data output 81 59 b8 65 53 tms j - tag test mode state input / output 80 58 a8 64 52 traceclk trace clk output of etm 86 64 c7 - - traced0 trace data output of etm 82 60 c8 - - traced1 83 61 d9 - - traced2 84 62 a7 - - traced3 85 63 b7 - - trstx j - tag test reset i nput 77 55 a9 61 49 external bus mad00 _1 e xternal bus interface address bus 31 9 h5 21 - mad01 _1 32 10 l6 22 - mad02 _1 39 17 k6 29 - mad03 _1 40 18 j6 30 - mad04 _1 41 19 l7 31 - mad05 _1 42 20 k7 32 - mad06 _1 43 21 h6 33 - mad07 _1 44 22 j7 34 - mad08 _1 45 23 k8 35 - mad09 _1 53 31 j10 43 - mad10 _1 54 32 j8 44 - mad11 _1 55 33 h10 45 - mad12 _1 56 34 h9 46 - mad13 _1 57 35 h7 47 - mad14 _1 58 36 g10 48 - mad15_1 59 37 g9 49 - mad16 _1 63 41 g8 53 - mad17 _1 64 42 f10 54 - mad18 _1 65 43 f9 55 - mad19 _1 66 44 e11 56 - mad20 _1 67 45 e10 - - mad21 _1 68 46 f8 - - mad2 2_1 69 47 e9 - - mad23 _1 70 48 d11 - - mad24 _1 74 52 c10 60 - d a t a s h e e t 30 mb9a110a - ds706 - 00011 - 3v0 - e, december 1 6 , 2014 confidential module pin name funct ion pin no lqfp - 100 qfp - 100 bga - 1 12 lqfp - 80 lq fp - 64 qfn - 64 external bus mcsx0 _1 external bus interface chip select output pin 88 66 a6 68 - mcsx1 _1 87 65 d7 67 - mcsx2 _1 86 64 c7 - - mcsx3 _1 85 63 b7 - - mcsx4 _1 83 61 d9 - - mcsx5 _1 82 60 c8 - - mcsx6 _1 79 57 b11 63 - mcsx7 _1 77 55 a9 61 - mdqm0 _1 external bus interface byte mask signal output 90 68 c6 70 - mdqm1 _1 91 69 a5 71 - moex _1 external bus interf ace read enable signal for sram 94 72 c5 74 - mwex _1 external bus interface write enable signal for sram 93 71 d6 73 - m a data0 0_1 e xternal bus interface data bus 2 80 c1 2 - m a data0 1_1 3 81 c2 3 - m a data0 2_1 4 82 b3 4 - m a data0 3_1 5 83 d1 5 - m a data0 4_1 6 84 d2 6 - m a data0 5_1 7 85 d3 7 - m a data0 6_1 8 86 d5 8 - m a data0 7_1 9 87 e1 9 - m a data0 8_1 10 88 e2 10 - m a data0 9_1 11 89 e3 11 - m a data 10_1 12 90 e4 12 - m a data 11_1 13 91 f1 - - m a data 12_1 14 92 f2 - - m a data 13_1 15 93 f3 - - m a data 14_1 16 94 g1 - - m a data 15_1 17 95 g2 - - male_1 address latch enable signal for multiplex 89 67 b6 69 - mrdy_1 external rdy input signal 96 74 c4 76 - mclkout_1 external bus clock output 84 62 a7 66 - d a t a s h e e t december 1 6 , 2014 , mb9a110a - ds706 - 00011 - 3v0 - e 31 confidential module pin name function pin no lqfp - 100 qfp - 100 bga - 1 12 lqfp - 80 lq fp - 64 qf n - 64 external interrupt int00_0 external interrupt request 00 input pin 2 80 c1 2 2 int00_1 82 60 c8 - - int00_2 87 65 d7 67 54 int01_0 external interrupt request 0 1 input pin 3 81 c2 3 3 int01_1 83 61 d9 - - int02_0 external interrupt reque st 0 2 input pin 4 82 b3 4 4 int02_1 53 31 j10 43 35 int03_0 external interrupt request 0 3 input pin 93 71 d6 73 - int03_1 56 34 h9 46 38 int03_2 9 87 e1 9 5 int04_0 external interrupt request 04 input pin 12 90 e4 12 8 int04_1 59 37 g9 49 40 int04_2 10 88 e2 10 6 int05_0 external interrupt request 05 input pin 74 52 c10 60 - int05_1 65 43 f9 55 - int05_2 11 89 e3 11 7 int06_1 external interrupt request 0 6 input pin 73 51 c11 59 48 int06_2 45 23 k8 35 27 int07_2 external i nterrupt request 0 7 input pin 5 83 d1 5 - int08_1 external interrupt request 0 8 input pin 14 92 f2 - - int08_2 8 86 d5 8 - int09_1 external interrupt request 0 9 input pin 15 93 f3 - - int10_1 external interrupt request 10 input pin 16 94 g1 - - int11_1 external interrupt request 11 input pin 17 95 g2 - - int12_1 external interrupt request 12 input pin 27 5 j4 - - int13_1 external interrupt request 13 input pin 28 6 l5 - - int14_1 external interrupt request 14 input pin 39 17 k6 29 - int15 _1 external interrupt request 15 input pin 96 74 c4 76 60 nmix non - maskable interrupt input 92 70 b5 72 57 d a t a s h e e t 32 mb9a110a - ds706 - 00011 - 3v0 - e, december 1 6 , 2014 confidential module pin name function pin no lqfp - 100 qfp - 100 bga - 1 12 lqfp - 80 lq fp - 64 qfn - 64 gpio p00 general - purpose i/o port 0 77 55 a9 61 49 p01 78 56 b9 62 50 p02 79 57 b11 63 51 p03 80 58 a8 64 52 p04 81 59 b8 65 53 p05 82 60 c8 - - p06 83 61 d9 - - p07 84 62 a7 66 - p08 85 63 b7 - - p09 86 64 c7 - - p0a 87 65 d7 67 54 p0b 88 66 a6 68 55 p0c 89 67 b6 69 56 p0d 90 68 c6 70 - p0e 91 69 a5 71 - p0f 92 70 b5 72 57 p10 general - purpose i/o port 1 52 30 j11 42 34 p11 53 31 j10 43 35 p12 54 32 j8 44 36 p13 55 33 h10 45 37 p14 56 34 h9 46 38 p15 57 35 h7 47 39 p16 58 36 g10 48 - p17 59 37 g9 49 40 p18 63 41 g8 53 44 p19 64 42 f10 54 45 p1a 65 43 f9 55 - p1b 66 44 e11 56 - p1c 67 45 e10 - - p1d 68 46 f8 - - p1e 69 47 e9 - - p1f 70 48 d11 - - p20 general - purpose i/o port 2 74 52 c10 60 - p21 73 51 c11 59 48 p 22 72 50 e8 58 47 p23 71 49 d10 57 46 d a t a s h e e t december 1 6 , 2014 , mb9a110a - ds706 - 00011 - 3v0 - e 33 confidential module pin name function pin no lqfp - 100 qfp - 100 bga - 1 12 lqfp - 80 lq fp - 64 qfn - 64 gpio p30 general - purpose i/o port 3 9 87 e1 9 5 p31 10 88 e2 10 6 p32 11 89 e3 11 7 p33 12 90 e4 12 8 p34 1 3 91 f1 - - p35 14 92 f2 - - p36 15 93 f3 - - p37 16 94 g1 - - p38 17 95 g2 - - p39 18 96 f4 13 9 p3a 19 97 g3 14 10 p3b 20 98 h1 15 11 p3c 21 99 h2 16 12 p3d 22 100 g4 17 13 p3e 23 1 h3 18 14 p3f 24 2 j2 19 15 p40 genera l - purpose i/o port 4 27 5 j4 - - p41 28 6 l5 - - p42 29 7 k5 - - p43 30 8 j5 - - p44 31 9 h5 21 - p45 32 10 l6 22 - p46 36 14 l3 26 19 p47 37 15 k3 27 20 p48 39 17 k6 29 - p49 40 18 j6 30 22 p4a 41 19 l7 31 23 p4b 42 20 k7 32 24 p4c 43 21 h6 33 25 p4d 44 22 j7 34 26 p4e 45 23 k8 35 27 p50 general - purpose i/o port 5 2 80 c1 2 2 p51 3 81 c2 3 3 p52 4 82 b3 4 4 p53 5 83 d1 5 - p54 6 84 d2 6 - p55 7 85 d3 7 - p56 8 86 d5 8 - p60 general - purpose i/o port 6 96 74 c4 76 60 p61 95 73 b4 75 59 p62 94 72 c5 74 58 p6 3 93 71 d6 73 - p80 general - purpose i/o port 8 98 76 a3 78 62 p81 99 77 a2 79 63 pe0 general - purpose i/o port e 46 24 k9 36 28 pe2 48 26 l9 38 30 pe3 49 27 l10 39 31 d a t a s h e e t 34 mb9a110a - ds706 - 00011 - 3v0 - e, december 1 6 , 2014 confidential m odule pin name function pin no lqfp - 100 qfp - 100 bga - 1 12 lqfp - 80 lq fp - 64 qfn - 64 multi function serial 0 sin0_0 multifunction serial interface ch.0 input pin 73 51 c11 59 48 sin0_1 56 34 h9 46 - sot0_0 (sda0_0) multifunction serial interface ch.0 output pin . this pin operates as sot0 when it is used in a uart/csio /lin (operation modes 0 to 3 ) and as sda0 when it is used in an i 2 c (operation mode 4). 72 50 e8 58 47 sot0_1 (sda0_1) 57 35 h7 47 - sck0_0 (scl0_0) multifunction serial interfac e ch.0 clock i/o pin . this pin operates as sck0 when it is used in a csio (operation mode 2 ) and as scl0 when it is used in an i 2 c (operation mode 4). 71 49 d10 57 46 sck0_1 (scl0_1) 58 36 g10 48 - multi function serial 1 sin1_1 multifunction serial in terface ch.1 input pin 53 31 j10 43 35 sot1_1 (sda1_1) multifunction serial interface ch.1 output pin . this pin operates as sot1 when it is used in a uart/csio /lin (operation modes 0 to 3 ) and as sda1 when it is used in an i 2 c (operation mode 4). 54 32 j 8 44 36 sck1_1 (scl1_1) multifunction serial interface ch. 1 clock i/o pin . this pin operates as sck 1 when it is used in a csio (operation mode 2 ) and as scl 1 when it is used in an i 2 c (operation mode 4). 55 33 h10 45 37 d a t a s h e e t december 1 6 , 2014 , mb9a110a - ds706 - 00011 - 3v0 - e 35 confidential module pin name function pin no lqfp - 100 qfp - 100 bga - 1 12 lqfp - 80 lq fp - 64 qfn - 64 multi function serial 2 sin2_ 2 multifunction serial interface ch.2 input pin 59 37 g9 49 40 sot2_ 2 (sda2_ 2 ) multifunction serial interface ch.2 output pin . this pin operates as sot2 when it is u sed in a uart/csio /lin (operation modes 0 to 3 ) and as sda2 when it is used in an i 2 c (operation mode 4). 63 41 g8 53 44 sck2_ 2 (scl2_ 2 ) multifunction serial interface ch.2 clock i/o pin . this pin operates as sck2 when it is used in a csio (operation mod e 2 ) and as scl2 when it is used in an i 2 c (operation mode 4). 64 42 f10 54 45 multi function serial 3 sin3_ 1 multifunction serial interface ch.3 input pin 2 80 c1 2 2 sin3_ 2 39 17 k6 29 - sot3_ 1 (sda3_ 1 ) multifunction serial interface ch.3 output pi n . this pin operates as sot3 when it is used in a uart/csio /lin (operation modes 0 to 3 ) and as sda3 when it is used in an i 2 c (operation mode 4). 3 81 c2 3 3 sot3_ 2 (sda3_ 2 ) 40 18 j6 30 - sck3_ 1 (scl3_ 1 ) multifunction serial interface ch.3 clock i/o pin . this pin operates as sck3 when it is used in a csio (operation mode 2 ) and as scl3 when it is used in an i 2 c (operation mode 4). 4 82 b3 4 4 sck3_ 2 (scl3_ 2 ) 41 19 l7 31 - d a t a s h e e t 36 mb9a110a - ds706 - 00011 - 3v0 - e, december 1 6 , 2014 confidential module pin name function pin no lqfp - 100 qfp - 100 bga - 1 12 lqfp - 80 l q fp - 64 qfn - 64 multi function serial 4 sin4_0 multifunction serial interface ch.4 input pin 87 65 d7 67 54 sin4_1 65 43 f9 55 - sin4_2 82 60 c8 - - sot4_0 (sda4_0) multifunction serial interface ch.4 output pin . this pin operates as sot4 when it is used in a uart/csio /lin (operation modes 0 to 3 ) and as sda4 when it is used in an i 2 c (operation mode 4). 88 66 a6 68 55 sot4_1 (sda4_1) 66 44 e11 56 - sot4_2 (sda4_2) 83 61 d9 - - sck4_0 (scl4_0) multifunction serial interface ch.4 clock i/o p in . this pin operates as sck4 when it is used in a csio (operation mode 2 ) and as scl4 when it is used in an i 2 c (operation mode 4). 89 67 b6 69 56 sck4_1 (scl4_1) 67 45 e10 - - sck4_2 (scl4_2) 84 62 a7 - - rts4_0 multifunction serial interface ch. 4 rts output pin 90 68 c6 70 - rts4_1 69 47 e9 - - rts4_2 86 64 c7 - - cts4_0 multifunction serial interface ch.4 cts input pin 91 69 a5 71 - cts4_1 68 46 f8 - - cts4_2 85 63 b7 - - multi function serial 5 sin5_0 multifunction serial interfa ce ch.5 input pin 96 74 c4 76 60 sin5_2 15 93 f3 - - sot5_0 (sda5_0) multifunction serial interface ch.5 output pin . this pin operates as sot5 when it is used in a uart/csio /lin (operation modes 0 to 3 ) and as sda5 when it is used in an i 2 c (operation mode 4). 95 73 b4 75 59 sot5_2 (sda5_2) 16 94 g1 - - sck5_0 (scl5_0) multifunction serial interface ch.5 clock i/o pin . this pin operates as sck5 when it is used in a csio (operation mode 2 ) and as scl5 when it is used in an i 2 c (operation mode 4). 9 4 72 c5 74 58 sck5_2 (scl5_2) 17 95 g2 - - d a t a s h e e t december 1 6 , 2014 , mb9a110a - ds706 - 00011 - 3v0 - e 37 confidential module pin name function pin no lqfp - 100 qfp - 100 bga - 1 12 lqfp - 80 lq fp - 64 qfn - 64 multi function serial 6 sin6_0 multifunction serial interface ch.6 input pin 5 83 d1 5 - sin6_1 12 90 e4 12 8 s ot6_0 (sda6_0) multifunction serial interface ch.6 output pin . this pin operates as sot6 when it is used in a uart/csio /lin (operation modes 0 to 3 ) and as sda6 when it is used in an i 2 c (operation mode 4). 6 84 d2 6 - sot6_1 (sda6_1) 11 89 e3 11 7 sc k6_0 (scl6_0) multifunction serial interface ch.6 clock i/o pin . this pin operates as sck6 when it is used in a csio (operation mode 2 ) and as scl6 when it is used in an i 2 c (operation mode 4). 7 85 d3 7 - sck6_1 (scl6_1) 10 88 e2 10 6 multi function s erial 7 sin7_ 1 multifunction serial interface ch.7 input pin 45 23 k8 35 27 sot7_ 1 (sda7_ 1 ) multifunction serial interface ch.7 output pin . this pin operates as sot7 when it is used in a uart/csio /lin (operation modes 0 to 3 ) and as sda7 when it is used in an i 2 c (operation mode 4). 44 22 j7 34 26 sck7_ 1 (scl7_ 1 ) multifunction serial interface ch.7 clock i/o pin . this pin operates as sck7 when it is used in a csio (operation mode 2 ) and as scl7 when it is used in an i 2 c (operation mode 4). 43 21 h6 33 2 5 d a t a s h e e t 38 mb9a110a - ds706 - 00011 - 3v0 - e, december 1 6 , 2014 confidential module pin name function pin no lqfp - 100 qfp - 100 bga - 1 12 lqfp - 80 lq fp - 64 qfn - 64 multi function timer 0 dtti0x_0 input signal of waveform generator to control outputs rto00 to rto05 of multi - function timer 0 18 96 f4 13 9 dtti0x_1 69 47 e 9 - - frck0_0 16 - bit free - run timer external clock input pin 13 91 f1 - - frck0_1 70 48 d11 - - frck0_ 2 53 31 j10 43 35 ic00_0 16 - bit input capture input pin of multi - function timer 0 . icxx describes channel number. 17 95 g2 - - ic00_1 65 43 f 9 55 - ic00_ 2 54 32 j8 44 36 ic01_0 16 94 g1 - - ic01_1 66 44 e11 56 - ic01_ 2 55 33 h10 45 37 ic02_0 15 93 f3 - - ic02_1 67 45 e10 - - ic02_ 2 56 34 h9 46 38 ic03_0 14 92 f2 - - ic03_1 68 46 f8 - - ic03_ 2 57 35 h7 47 39 rto00 _0 (ppg00_0) waveform generator output of multi - function timer 0 . this pin operates as ppg00 when it is used in ppg 0 output mode . 19 97 g3 14 10 rto00_1 (ppg00_1) 71 49 d10 - - rto01_0 (ppg00_0) waveform generator output of multi - function timer 0 . th is pin operates as ppg00 when it is used in ppg 0 output mode . 20 98 h1 15 11 rto02_0 (ppg02_0) waveform generator output of multi - function timer 0 . this pin operates as ppg02 when it is used in ppg 0 output mode . 21 99 h2 16 12 rto03_0 (ppg02_0) wavef orm generator output of multi - function timer 0 . this pin operates as ppg02 when it is used in ppg 0 output mode . 22 100 g4 17 13 rto04_0 (ppg04_0) waveform generator output of multi - function timer 0 . this pin operates as ppg04 when it is used in ppg 0 ou tput mode . 23 1 h3 18 14 rto05_0 (ppg04_0) waveform generator output of multi - function timer 0 . this pin operates as ppg04 when it is used in ppg 0 output mode . 24 2 j2 19 15 d a t a s h e e t december 1 6 , 2014 , mb9a110a - ds706 - 00011 - 3v0 - e 39 confidential module pin name function pin no lqfp - 100 qfp - 100 bga - 1 12 lqfp - 80 lq fp - 64 qfn - 64 multi function timer 1 dtti1x_0 input signal of waveform generator to control outputs rto 10 to rto 15 of multi - function timer 1 8 86 d5 8 - dtti1x_1 39 17 k6 29 - frck1_0 16 - bit free - run timer ch.1 external clock input pin 87 65 d7 67 - frck1_1 44 22 j7 34 - ic10_0 16 - bit input capture input pin of multi - function timer 1 . icxx des cribes channel number. 88 66 a6 68 - ic10_1 40 18 j6 30 - ic11_0 89 67 b6 69 - ic11_1 41 19 l7 31 - ic12_0 90 68 c6 70 - ic12_1 42 20 k7 32 - ic13_0 91 69 a5 71 - ic13_1 43 21 h6 33 - rto10_0 (ppg10_0) waveform generator output of multi - function timer 1 . this pin operates as ppg10 when it is used in ppg 1 output mode . 2 80 c1 2 - rto10_1 (ppg10_1) 27 5 j4 - - rto11_0 (ppg10_0) wav eform generator output of multi - function timer 1 . this pin operates as ppg10 when it is used in ppg 1 output mode . 3 81 c2 3 - rto11_1 (ppg10_1) 28 6 l5 - - rto12_0 (ppg12_0) waveform generator output of multi - function timer 1 . this pin operates as pp g12 when it is used in ppg 1 output mode . 4 82 b3 4 - rto12_1 (ppg12_1) 29 7 k5 - - rto13_0 (ppg12_0) waveform generator output of multi - function timer 1 . this pin operates as ppg12 when it is used in ppg 1 output mode . 5 83 d1 5 - rto13_1 (ppg12_1) 30 8 j5 - - rto14_0 (ppg14_0) waveform generator output of multi - function timer 1 . this pin operates as ppg14 when it is used in ppg 1 output mode . 6 84 d2 6 - rto14_1 (ppg14_1) 31 9 h5 21 - rto15_0 (ppg14_0) waveform generator output of multi - fun ction timer 1 . this pin operates as ppg14 when it is used in ppg 1 output mode . 7 85 d3 7 - rto15_1 (ppg14_1) 32 10 l6 22 - d a t a s h e e t 40 mb9a110a - ds706 - 00011 - 3v0 - e, december 1 6 , 2014 confidential module pin name function pin no lqfp - 100 qfp - 100 bga - 1 12 lqfp - 80 lq fp - 64 qfn - 64 quadrature position/ revolution cou nter 0 ain0_0 q prc ch.0 ain input pin 9 87 e1 9 5 ain0_1 40 18 j6 30 22 ain0_2 2 80 c1 2 2 bin0_0 q prc ch.0 bin input pin 10 88 e2 10 6 bin0_1 41 19 l7 31 23 bin0_2 3 81 c2 3 3 zin0_0 q prc ch.0 zin input pin 11 89 e3 11 7 zin0_1 42 20 k 7 32 24 zin0_2 4 82 b3 4 4 quadrature position/ revolution counter 1 ain1_1 q prc ch.1 ain input pin 74 52 c10 60 - ain1_2 43 21 h6 33 25 bin1_1 q prc ch.1 bin input pin 73 51 c11 59 - bin1_2 44 22 j7 34 26 zin1_1 q prc ch.1 zin input pin 72 50 e8 58 - zin1_2 45 23 k8 35 27 d a t a s h e e t december 1 6 , 2014 , mb9a110a - ds706 - 00011 - 3v0 - e 41 confidential module pin name function pin no lqfp - 100 qfp - 100 bga - 1 12 lqfp - 80 lq fp - 64 qfn - 64 reset initx external reset input . a reset is valid when initx= " l " 38 16 k4 28 21 mode md0 mode 0 pin . during normal operation , md0= " l " must be input. during serial programming to flash memory, md0= " h " must be input. 47 25 l8 37 29 md1 mode 1 pin . during serial programming to flash memory, md 1 = " l " must be input. 46 24 k9 36 28 power vcc power supply p i n 1 79 b1 1 1 vcc po wer supply p in 26 4 j1 - - vcc power supply pin 35 13 k1 25 18 vcc power supply pin 51 29 k11 41 33 vcc power supply pin 76 54 a10 - - vcc power supply pin 97 75 a4 77 61 gnd vss gnd p in - - b2 - - vss gnd pin 25 3 l1 20 16 vss gnd pin - - k2 - - vss gnd pin - - j3 - - vss gnd pin - - h4 - - vss gnd pin 34 12 l4 24 - vss gnd pin 50 28 l11 40 32 vss gnd pin - - k10 - - vss gnd pin - - j9 - - vss gnd pin - - h8 - - vss gnd pin - - b10 - - vss gnd pin - - c9 - - vss gnd pin 75 53 a11 - - vss gnd pin - - d8 - - vss gnd pin - - d4 - - vss gnd pin - - c3 - - vss gnd pin 100 78 a1 80 64 clock x0 main clock (oscillation) input pin 48 26 l9 38 30 x0a sub clock (oscillation) input pin 36 14 l3 26 19 x1 main clock (oscillat ion) i/o pin 49 27 l10 39 31 x1a sub clock (oscillation) i/o pin 37 15 k3 27 20 crout _0 built - in high - speed cr - osc clock output port 74 52 c10 60 - crout _1 92 70 b5 72 57 analog power avcc a/d converter analog power supply pin 60 38 h11 50 41 avrh a/d converter analog reference voltage input pin 61 39 f11 51 42 analog gnd avss a/d converter gnd pin 62 40 g11 52 43 c pin c power supply stabilization capacity pin 33 11 l2 23 17 d a t a s h e e t 42 mb9a110a - ds706 - 00011 - 3v0 - e, december 1 6 , 2014 confidential ? i/o circuit type type circuit remarks a ? it is possible to select the main oscillation / gpio function when the main oscillation is selected. ? oscillation feedback resistor : approximately 1m ? with standby mode c ontrol when the gpio is selected. ? cmos level output. ? cmos level hysteresis input ? with pull - up resistor control ? with standby mode control ? p ull - up resistor : approximately 50k ? i oh = - 4ma, i ol = 4ma b ? cmos level hysteresis input ? p ull - up resistor : approximately 50k p - ch p - ch n - ch r r p - ch p - ch n - ch x0 x1 pull - up resistor feedback resistor pull - up resistor pull - up resistor d igital in put digital output digital output pull - up resistor control digital input standby mode control clock input standby mode control digital input standby mode control digital output digital output pull - up resistor control d a t a s h e e t december 1 6 , 2014 , mb9a110a - ds706 - 00011 - 3v0 - e 43 confidential type circuit remarks c ? open drain output ? cmos level hysteresis input d ? it is possible to select the sub oscillation / gpio function when the sub oscillation is selected. ? oscillation feedback resistor : approximately 5m ? with standby mode control when the gpio is selected. ? cmos level output. ? cmos l evel hysteresis input ? with pull - up resistor control ? with standby mode control ? p ull - up resistor : approximately 50k ? i oh = - 4ma, i ol = 4ma p - ch p - ch n - ch r r p - ch p - ch n - ch x0 a x1 a pull - up resistor feedback resistor pull - up resistor digital input digital out put digital output digital output pull - up resistor control digital input standby mode control clock input standby mode control digital input standby mode control digital output digital output pull - up re sistor control n-ch d a t a s h e e t 44 mb9a110a - ds706 - 00011 - 3v0 - e, december 1 6 , 2014 confidential type circuit remarks e ? cmos level output ? cmos level hysteresis input ? with pull - up resistor control ? with s tandby mode control ? p ull - up resistor : approximately 50k ? i oh = - 4ma, i ol = 4ma ? when this pin is used as an i2c pin, the digital output p - ch transistor is always off ? +b input is available f ? cmos level output ? cmos level hyst eresis input ? with input control ? analog input ? with pull - up resistor control ? with standby mode control ? p ull - up resistor : approximately 50k ? ioh = - 4ma, iol = 4ma ? when this pin is used as an i2c pin, the digital output p - ch transistor is always off ? +b input is available standby mode control digital output pull - up resistor control digital output di gital input p - ch p - ch n - ch digital output digital output pull - up resistor control input control standby mode control analog input digital input p - ch p - ch n - ch r r d a t a s h e e t december 1 6 , 2014 , mb9a110a - ds706 - 00011 - 3v0 - e 45 confidential type circuit remarks g ? cmos level output ? cmos level hysteresis input ? with pull - up resistor control ? with standby mode control ? p ull - up resistor : approximately 50k ? i oh = - 12 ma, i ol = 12 ma ? +b input is available h ? cmos level output ? cmos level hysteresis input ? with standby mode control ? i oh = - 20.5ma, i ol = 18.5ma standby mode control digital output digital output digital input n - ch standby mode control digital output pull - up resistor control digital ou tput digital input p - ch p - ch n - ch r r d a t a s h e e t 46 mb9a110a - ds706 - 00011 - 3v0 - e, december 1 6 , 2014 confidential type circuit remarks i ? cmos level output ? cmos level hysteresis input ? 5v tolerant ? with standby mod e control ? i oh = - 4 ma, i ol = 4 ma ? when this pin is used as an i2c pin, the digital output p - ch transistor is always off j cmos level hysteresis input digital in put standby mode control digital output digital output r p-ch n-ch mode input d a t a s h e e t december 1 6 , 2014 , mb9a110a - ds706 - 00011 - 3v0 - e 47 confident ial ? handling precautions any semiconductor devices have inherently a certain rate of failure. the possibility of failure is greatly affected by the conditions in which they are used (circuit conditions, environmental conditions, etc.). this page describes prec autions that must be observed to minimize the chance of failure and to obtain higher reliability from your spansion semiconductor devices. 1. precautions for product design this section describes precautions when designing electronic equipment using semicondu ctor devices. absolute maximum ratings semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of certain established limits, called absolute maximum ratings. do not exceed these ratings. re commended operating conditions recommended operating conditions are normal operating ranges for the semiconductor device. all the device's electrical characteristics are warranted when operated within these ranges. always use semiconductor devices within t he recommended operating conditions. operation outside these ranges may adversely affect reliability and could result in device failure. no warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. user s considering application outside the listed conditions are advised to contact their sales representative beforehand. processing and protection of pins these precautions must be followed when handling the pins which connect semiconductor devices to power s upply and input/output functions. (1) preventing over - voltage and over - current conditions exposure to voltage or current levels in excess of maximum ratings at any pin is likely to cause deterioration within the device, and in extreme cases leads to perma nent damage of the device. try to prevent such overvoltage or over - current conditions at the design stage. (2) protection of output pins shorting of output pins to supply pins or other output pins, or connection to large capacitance can cause large curren t flows. such conditions if present for extended periods of time can damage the device. therefore, avoid this type of connection. (3) handling of unused input pins unconnected input pins with very high impedance levels can adversely affect stability of op eration. such pins should be connected through an appropriate resistance to a power supply pin or ground pin. latch - up semiconductor devices are constructed by the formation of p - type and n - type areas on a substrate. when subjected to abnormally high volta ges, internal parasitic pnpn junctions (called thyristor structures) may be formed, causing large current levels in excess of several hundred ma to flow continuously at the power supply pin. this condition is called latch - up. caution: the occurrence of lat ch - up not only causes loss of reliability in the semiconductor device, but can cause injury or damage from high heat, smoke or flame. to prevent this from happening, do the following: (1) be sure that voltages applied to pins do not exceed the absolute ma ximum ratings. this should include attention to abnormal noise, surge levels, etc. (2) be sure that abnormal current flows do not occur during the power - on sequence. code: ds00 - 00004 - 3e d a t a s h e e t 48 mb9a110a - ds706 - 00011 - 3v0 - e, december 1 6 , 2014 confidential observance of safety regulations and standards most countries in the world have established standards and regulations regarding safety, protection from electromagnetic interference, etc. customers are requested to observe applicable regulations and standards in the design of products. fail - safe design any semiconductor dev ices have inherently a certain rate of failure. you must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over - current levels and other abnormal operating conditions. precautions related to usage of devices spansion semiconductor devices are intended for use in standard applications (computers, office automation and other office equipment, industrial, communications, and m easurement equipment, personal or household devices, etc.). caution: customers considering the use of our products in special applications where failure or abnormal operation may directly affect human lives or cause physical injury or property damage, or w here extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult with sales representatives before s uch use. the company will not be responsible for damages arising from such use without prior approval. 2. precautions for package mounting package mounting may be either lead insertion type or surface mount type. in either case, for heat resistance during so ldering, you should only mount under spansion 's recommended conditions. for detailed information about mount conditions, contact your sales representative. lead insertion type mounting of lead insertion type packages onto printed circuit boards may be done by two methods: direct soldering on the board, or mounting by using a socket. direct mounting onto boards normally involves processes for inserting leads into through - holes on the board and using the flow soldering (wave soldering) method of applying liqu id solder. in this case, the soldering process usually causes leads to be subjected to thermal stress in excess of the absolute ratings for storage temperature. mounting processes should conform to spansion recommended mounting conditions. if socket mounti ng is used, differences in surface treatment of the socket contacts and ic lead surfaces can lead to contact deterioration after long periods. for this reason it is recommended that the surface treatment of socket contacts and ic leads be verified before m ounting. surface mount type surface mount packaging has longer and thinner leads than lead - insertion packaging, and therefore leads are more easily deformed or bent. the use of packages with higher pin counts and narrower pin pitch results in increased sus ceptibility to open connections caused by deformed pins, or shorting due to solder bridges. you must use appropriate mounting techniques. spansion recommends the solder reflow method, and has established a ranking of mounting conditions for each product. u sers are advised to mount packages in accordance with spansion ranking of recommended conditions. d a t a s h e e t december 1 6 , 2014 , mb9a110a - ds706 - 00011 - 3v0 - e 49 confident ial lead - free packaging caution: when ball grid array (bga) packages with sn - ag - cu balls are mounted using sn - pb eutectic soldering, junction strength may be redu ced under some conditions of use. storage of semiconductor devices because plastic chip packages are formed from plastic resins, exposure to natural environmental conditions will cause absorption of moisture. during mounting, the application of heat to a p ackage that has absorbed moisture can cause surfaces to peel, reducing moisture resistance and causing packages to crack. to prevent, do the following: (1) avoid exposure to rapid temperature changes, which cause moisture to condense inside the product. st ore products in locations where temperature changes are slight. (2) use dry boxes for product storage. products should be stored below 70% relative humidity, and at temperatures between 5 c and 30 c . when you open dry package that recommends humidity 40% to 70% relative humidity. (3) when necessary, spansion packages semiconductor devices in highly moisture - resistant aluminum laminate bags, with a silica gel desiccant. devices should be sealed in their aluminum laminate bags for storage. (4) avoid storing packages where they are exposed to corrosive gases or high levels of dust. baking packages that have absorbed moisture may be de - moisturized by baking (heat drying). follow the spansion recommended conditions for baking. condition: 125 c /24 h static electr icity because semiconductor devices are particularly susceptible to damage by static electricity, you must take the following precautions: (1) maintain relative humidity in the working environment between 40% and 70%. use of an apparatus for ion generation may be needed to remove electricity. (2) electrically ground all conveyors, solder vessels, soldering irons and peripheral equipment. (3) eliminate static body electricity by the use of rings or bracelets connected to ground through high resistance (on th e level of 1 m ). wearing of conductive clothing and shoes, use of conductive floor mats and other measures to minimize shock loads is recommended. (4) ground all fixtures and instruments, or protect with anti - static measures. (5) avoid the use of styrofoam or other hi ghly static - prone materials for storage of completed board assemblies. d a t a s h e e t 50 mb9a110a - ds706 - 00011 - 3v0 - e, december 1 6 , 2014 confidential 3. precautions for use environment reliability of semiconductor devices depends on ambient temperature and other conditions as described above. for reliable performance, do the following: (1) humidity prolonged use in high humidity can lead to leakage in devices as well as printed circuit boards. if high humidity levels are anticipated, consider anti - humidity processing. (2) discharge of static electricity when high - voltage charges exist close to semiconductor devices, discharges can cause abnormal operation. in such cases, use anti - static measures or processing to prevent discharges. (3) corrosive gases, dust, or oil exposure to corrosive gases or contact with dust or oil may lead to ch emical reactions that will adversely affect the device. if you use devices in such conditions, consider ways to prevent such exposure or to protect the devices. (4) radiation, including cosmic radiation most devices are not designed for environments invol ving exposure to radiation or cosmic radiation. users should provide shielding as appropriate. (5) smoke, flame caution: plastic molded devices are flammable, and therefore should not be used near combustible substances. if devices begin to smoke or burn, there is danger of the release of toxic gases. customers considering the use of spansion products in other special environmental conditions should consult with sales representatives. please check the latest handling precautions at the following url. htt p:// www.spansion.com /fj documents/fj/datasheet / e - ds/ds00 - 00004 .pdf d a t a s h e e t december 1 6 , 2014 , mb9a110a - ds706 - 00011 - 3v0 - e 51 confident ial ? handling devices ? power supply pins in products with multiple v cc and v ss pins, respective pins at the same potential are interconnected within the device in order to prevent malfunctions such as latch - up. however, all of these pins should be connected externally to the power supply or ground lines in order to reduce electromagnetic emission levels, to prevent abnormal operation of strobe signals caused by the rise in the ground level, and to conform to the total output current rating. moreover, connect the current supply source with each power supply pin and gnd pin of this device at low impedance. it is also advisable that a ceramic capacitor of approximately 0.1 f be connected as a bypas s capacitor between each power supply pin and gnd pin , between avcc pin and avss pin near this device. ? stabilizing power supply voltage a malfunction may occur when the power supply voltage fluctuates rapidly even though the fluctuation is within the recom mended operating conditions of the vcc power supply voltage. as a rule, with voltage stabilization, suppress the voltage fluctuation so that the fluctuation in vcc ripple (peak - to - peak value) at the commercial frequency (50 hz/60 hz) does not exceed 10% of the vcc value in the recommended operating conditions, and the transient fluctuation rate does not exceed 0.1 v/s when there is a momentary fluctuation on switching the power supply. ? crystal oscillator circuit noise near the x0 /x1 and x0a/ x1 a pins may cause the device to malfunction. design the p rinted circuit board so tha t x0/ x1, x0a/ x1a pins , the crystal oscillator, and the bypass capacitor to ground are located as close to the device as possible. it is strongly recommended that the pc board artwork be designed such that the x0 /x1 and x0a/ x1a pi ns are surrounded by ground plane as this is expected to produce stable operation. evaluate oscillation of your using crystal oscillator by your mount board. ? using an external clock when using an external clock, the clock signal should be driven to the x0 , x0a pin only and the x1 ,x1a pin should be kept open. ? handling when using multi function serial pin as i 2 c pin if it is using the multi function serial pin as i 2 c pin s , p - ch transistor of digital output is always disable d . howev er, i 2 c pins need to keep the electrical characteristic like other pins and not to connect to the external i 2 c bus system with power off. ? example of using an external clock device x0 (x0a) x1 (x1a) open d a t a s h e e t 52 mb9a110a - ds706 - 00011 - 3v0 - e, december 1 6 , 2014 confidential ? c pin this series contains the regulator. be sure to connect a smoothing capacitor (c s ) for the regulator between the c pin and the gnd pin. please use a ceramic capacitor or a capacitor of equivalent frequency characteristics as a smoothing capacitor. however, some laminated ceramic capacitors have the characteristics of capacitance variation due to thermal fluctuation (f characteristics and y5v characteristics). please select the capacitor that meets the specifications in the operating conditions to use by evaluating the temperature characteristics of a capacitor. a smoothing capacitor of about 4.7 f would be recommended for this series. ? mode pins (md0) connect the md pin (md0) di rectly to v cc or v ss pins. design the printed circuit board such that the pull - up/down resist or stays low, as well as the distance between the mode pins and v cc pins or v ss pins is as short as possible and the connection impedance is low, when the pins are pulled - up/down such as for switching the pin level and rewriting the flash memory data. it is because of preventing the device erroneously switching to test mode due to noise. ? notes on power - on turn power on/off in the following order or at the same time . if not using the a/d converter, connect avcc = vcc and avss = vss. t urning on : vcc av cc avrh t urning off : avrh av cc vcc ? serial communication there is a possibility to receive wrong data due to the noise or other causes on the serial communicati on. therefore, design a printed circuit board so as to avoid noise. consider the case of receiving wrong data due to noise, perform error detection such as by applying a checksum of data at the end. if an error is detected, retransmit the data. ? differences in features among the products with different memory sizes and between f lash products and mask products the electric characteristics including power consumption, esd, latch - up, noise characteristics, and oscillation characteristics among the products with different memory sizes and between f lash products and mask products are different because chip layout and memory structures are different. if you are switching to use a different product of the same series, please make sure to evaluate the electric charac teristics. device c vss c s gnd d a t a s h e e t december 1 6 , 2014 , mb9a110a - ds706 - 00011 - 3v0 - e 53 confidential ? block diagram *1: for the mb9a f111l a /m a , f112l a /m a , mb9a f114l a /m a , mb9af 1 15m a and mb9af 1 16m a , etm is not available. * 2 : for the mb9a f111l a , f112l a and mb9a f114l a , the external bus interface and 12 - bit a/d converter (unit 2) are not available. and the m ulti - function serial interface does not support hardware flow control in these products. a h b - a p b b r i d g e : a p b 1 ( m a x 4 0 m h z ) f l a s h i / f c o r t e x - m 3 c o r e @ 4 0 m h z ( m a x ) c l o c k r e s e t g e n e r a t o r d u a l - t i m e r w a t c h d o g t i m e r ( h a r d w a r e ) d m a c 8 c h m u l t i - f u n c t i o n t i m e r x 2 m u l t i - f u n c t i o n s e r i a l i / f 8 c h . ( w i t h f i f o c h . 4 t o 7 ) & h w f l o w c o n t r o l ( c h . 4 ) * 2 1 6 - b i t f r e e - r u n t i m e r 3 c h . 1 6 - b i t o u t p u t c o m p a r e 6 c h . 1 6 - b i t i n p u t c a p t u r e 4 c h . w a v e f o r m g e n e r a t o r 3 c h . a / d a c t i v a t i o n c o m p a r e 3 c h . 1 6 - b i t p p g 3 c h . w a t c h c o u n t e r u n i t 0 g p i o c s v l v d e x t e r n a l i n t e r r u p t c o n t r o l l e r 1 6 - p i n + n m i p o w e r - o n r e s e t t p i u * 1 r o m t a b l e e t m * 1 s r a m 0 8 / 1 6 k b y t e s w j - d p s r a m 1 8 / 1 6 k b y t e i d s y s m b 9 a f 1 1 1 l a / m a / n a , f 1 1 2 l a / m a / n a , f 1 1 4 l a / m a / n a , f 1 1 5 m a / n a , f 1 1 6 m a / n a b a s e t i m e r 1 6 - b i t 8 c h . / 3 2 - b i t 4 c h . n v i c w a t c h d o g t i m e r ( s o f t w a r e ) s e c u r i t y 1 2 - b i t a / d c o n v e r t e r x 3 u n i t 1 u n i t 2 * 2 t r s t x , t c k , t d i , t m s t r a c e d [ 3 : 0 ] , t r a c e c l k a n [ 1 5 : 0 ] t i o a [ 7 : 0 ] t i o b [ 7 : 0 ] i c 0 [ 3 : 0 ] d t t i [ 1 : 0 ] x r t o 0 [ 5 : 0 ] f r c k [ 1 : 0 ] c t d o s c k [ 7 : 0 ] s i n [ 7 : 0 ] s o t [ 7 : 0 ] i n t [ 1 5 : 0 ] n m i x p 0 [ f : 0 ] , p 1 [ f : 0 ] , . . . p x [ x : 0 ] i n i t x m o d e - c t r l i r q - m o n i t o r p i n - f u n c t i o n - c t r l m d [ 1 : 0 ] r e g u l a t o r q p r c 2 c h . a i n [ 1 : 0 ] b i n [ 1 : 0 ] z i n [ 1 : 0 ] l v d c t r l c r c a c c e l e r a t o r i c 1 [ 3 : 0 ] a d t g x r t s 4 c t s 4 e x t e r n a l b u s i / f * 2 m a d [ 2 4 : 0 ] m a d a t a [ 1 5 : 0 ] m c s x [ 7 : 0 ] , m o e x , m w e x , m a l e , m r d y , m c l k o u t , m d q m [ 1 : 0 ] r t o 1 [ 5 : 0 ] o n - c h i p f l a s h 6 4 / 1 2 8 / 2 5 6 / 3 8 4 / 5 1 2 k b y t e a h b - a h b b r i d g e a h b - a p b b r i d g e : a p b 0 ( m a x 4 0 m h z ) m u l t i - l a y e r a h b ( m a x 4 0 m h z ) a h b - a p b b r i d g e : a p b 2 ( m a x 4 0 m h z ) x 0 x 1 x 0 a p l l c l k c r 1 0 0 k h z s o u r c e c l o c k c r o u t m a i n o s c s u b o s c c r 4 m h z a v c c , a v s s , a v r h d a t a s h e e t 54 mb9a110a - ds706 - 00011 - 3v0 - e, december 1 6 , 2014 confidential ? memory size see " ? memory size " in " ? product lineup " to confirm the memory size . d a t a s h e e t december 1 6 , 2014 , mb9a110a - ds706 - 00011 - 3v0 - e 55 confidential ? m emory map ? memory map ( 1) peripherals area 0x41ff_ffff 0xffff_ffff 0xe010_0000 0x4006_1000 0xe000_0000 0x4006_0000 dmac 0x4005_0000 0x4003_f000 ext-bus i/f 0x4003_b000 0x4003_a000 watch counter 0x7000_0000 0x4003_9000 crc 0x4003_8000 mfs 0x6000_0000 0x4003_7000 0x4003_5000 lvd 0x4400_0000 0x4003_4000 0x4200_0000 0x4003_3000 gpio 0x4003_2000 reserved 0x4000_0000 0x4003_1000 int-req.read 0x4003_0000 exti 0x4002_f000 reserved 0x2400_0000 0x4002_e000 cr trim 0x2200_0000 0x4002_8000 0x4002_7000 a/dc 0x4002_6000 qprc 0x2008_0000 0x4002_5000 base timer 0x2000_0000 sram1 ppg 0x1ff8_0000 sram0 0x4002_2000 0x0010_2000 0x4002_1000 mft unit1 0x0010_0000 security/cr trim 0x4002_0000 mft unit0 0x4001_6000 0x4001_5000 dual timer 0x4001_3000 0x0000_0000 0x4001_2000 sw wdt 0x4001_1000 hw wdt 0x4001_0000 clock/reset 0x4000_1000 0x4000_0000 flash i/f reserved reserved cortex-m3 private peripherals reserved see the next page "nmemory map (2),(3)" for the memory size details. reserved reserved flash reserved reserved reserved reserved peripherals reserved 32mbytes bit band alias reserved reserved reserved reserved 32mbytes bit band alias reserved external device area d a t a s h e e t 56 mb9a110a - ds706 - 00011 - 3v0 - e, december 1 6 , 2014 confidential ? memory map ( 2) *: see " mb9 a310 a /1 1 0 a series flash programming m anual " for sector s tructure of flash. mb9af116ma/na mb9af115ma/na mb9af114la/ma/na 0x2008_0000 0x2008_0000 0x2008_0000 0x2000_4000 0x2000_4000 0x2000_4000 0x2000_0000 0x2000_0000 0x2000_0000 0x1fff_c000 0x1fff_c000 0x1fff_c000 0x0010_2000 0x0010_2000 0x0010_2000 0x0010_1000 cr trimming 0x0010_1000 cr trimming 0x0010_1000 cr trimming 0x0010_0000 security 0x0010_0000 security 0x0010_0000 security 0x0008_0000 0x0006_0000 0x0004_0000 0x0000_0000 sa4-7(8kbx4) 0x0000_0000 sa4-7(8kbx4) 0x0000_0000 sa4-7(8kbx4) flash 384kbytes sa10-11(64kbx2) reserved sram0 16kbytes sram1 16kbytes reserved sram1 16kbytes sram0 16kbytes flash 256kbytes sa8-9(48kbx2) sa8-9(48kbx2) sa8-9(48kbx2) reserved sram1 16kbytes sram0 16kbytes reserved reserved reserved reserved reserved reserved sa10-15(64kbx6) flash 512kbytes sa10-13(64kbx4) d a t a s h e e t december 1 6 , 2014 , mb9a110a - ds706 - 00011 - 3v0 - e 57 confidential ? memory map ( 3) * : see " mb9 a310 a /1 1 0 a series flash programming m anual " for sector s tructure of flash. mb9af112la/ma/na MB9AF111LA/ma/na 0x2008_0000 0x2008_0000 0x2000_2000 0x2000_2000 0x2000_0000 0x2000_0000 0x1fff_e000 0x1fff_e000 0x0010_2000 0x0010_2000 0x0010_1000 cr trimming 0x0010_1000 cr trimming 0x0010_0000 security 0x0010_0000 security 0x0002_0000 0x0001_0000 0x0000_0000 sa4-7(8kbx4) 0x0000_0000 sa4-7(8kbx4) reserved sram1 8kbytes reserved sram1 8kbytes reserved reserved flash 128kbytes sram0 8kbytes sram0 8kbytes flash 64kbytes reserved sa8-9(48kbx2) sa8-9(16kbx2) reserved d a t a s h e e t 58 mb9a110a - ds706 - 00011 - 3v0 - e, december 1 6 , 2014 confidential ? peripheral address map start address end address bus peripherals 0x4000_0000 h 0x4000_0fff h ahb flash memory i/f register 0x4000_1000 h 0x4000_ffff h res erved 0x4001_0000 h 0x4001_0fff h apb0 clock/reset control 0x4001_1000 h 0x4001_1fff h hardware watchdog timer 0x4001_2000 h 0x4001_2fff h software watchdog timer 0x4001_3000 h 0x4001_4fff h reserved 0x4001_5000 h 0x4001_5fff h dual - timer 0x4001_6000 h 0x40 01_ffff h reserved 0x4002_0000 h 0x4002_0fff h apb1 multi - function timer unit 0 0x4002_1000 h 0x4002_1fff h multi - function timer unit 1 0x4002_2000 h 0x4002_3fff h reserved 0x4002_4000 h 0x4002_4fff h ppg 0x4002_5000 h 0x4002_5fff h base timer 0x4002_6000 h 0 x4002_6fff h quadrature position/revolution counter (qprc) 0x4002_7000 h 0x4002_7fff h a/d converter 0x4002_8000 h 0x4002_dfff h reserved 0x4002_e000 h 0x4002_efff h built - in cr trimming 0x4002_f000 h 0x4002_ffff h reserved 0x4003_0000 h 0x4003_0fff h apb2 external interrupt 0x4003_1000 h 0x4003_1fff h interrupt source check register 0x4003_2000 h 0x4003_2fff h reserved 0x4003_3000 h 0x4003_3fff h gpio 0x4003_4000 h 0x4003_4fff h reserved 0x4003_5000 h 0x4003_5fff h low - voltage detector 0x4003_6000 h 0x4003_ 6fff h reserved 0x4003_7000 h 0x4003_7fff h reserved 0x4003_8000 h 0x4003_8fff h multi - function serial interface 0x4003_9000 h 0x4003_9fff h crc 0x4003_a000 h 0x4003_afff h watch counter 0x4003_b000 h 0x4003_efff h reserved 0x4003_f000 h 0x4003_ffff h exte rnal bus interface 0x4004_0000 h 0x4004_ffff h ahb reserved 0x4005_0000 h 0x4005_ffff h reserved 0x4006_0000 h 0x4006_0fff h dmac register 0x4006_1000 h 0x4006_1fff h reserved 0x4006_2000 h 0x4006_2fff h reserved 0x4006_3000 h 0x4006_3fff h reserved 0x4006 _4000 h 0x41ff_ffff h reserved d a t a s h e e t december 1 6 , 2014 , mb9a110a - ds706 - 00011 - 3v0 - e 59 confidential ? pin status in each cpu state the terms used for pin status have the following meanings. ? initx=0 this is the period when the initx pin is the " l " level. ? initx=1 this is the period when the initx pin is the " h " level. ? spl=0 this is the status that the standb y pin level setting bit (spl) in the standby mode control register (stb_ctl) is set to " 0 " . ? spl=1 this is the status that the standby pin level setting bit (spl) in the standby mode control register (stb_ctl) is set to " 1 " . ? input enabled indicates that the input function can be used. ? internal input fixed at " 0 " this is the status that the input function cannot be used. internal input is fixed at " l " . ? hi - z indicates that the pin drive transistor is disabled and the pin is put in the hi - z state. ? setting disab led indicates that the setting is disabled . ? maintain previous state maintains the state that was immediately prior to entering the current mode. if a built - in peripheral function is operating, the output follows the peripheral function. if the pin is being used as a port, that output is maintained. ? analog input is enabled indicates that the analog input is enabled. ? trace output indic ates that the trace function can be used . d a t a s h e e t 60 mb9a110a - ds706 - 00011 - 3 v0 - e, december 1 6 , 2014 confidential ? l ist of p in s tatus pin status type function group power - on reset or low - voltage de tection state initx input state device internal reset state run mode or sleep mode state timer mode or stop mode state power supply unstable power supply stable power supply stable power supply stable - initx=0 initx=1 initx=1 initx=1 - - - - spl= 0 spl=1 a gpio selected setting disabled setting disabled setting disabled maintain previous state maintain previous state hi - z/ internal input fixed at " 0 " main crystal oscillator input pin input enabled input enabled input enabled input enabled input enabled input enabled b gpio selected setting disabled setting disabled setting disabled maintain previous state maintain previous state hi - z/ internal input fixed at " 0 " main crystal oscillator output pin hi - z/ internal input fixed at " 0 " / o r input ena ble hi - z/ internal input fixed at " 0 " hi - z/ internal input fixed at " 0 " maintain previous state maintain previous state/ hi - z at oscillation stop * 1 / internal input fixed at " 0 " maintain previous state/ hi - z at oscillation stop * 1 / internal input fixed at " 0 " c initx input pin pull - up / i nput enabled pull - up / i nput enabled pull - up / i nput enabled pull - up / i nput enabled pull - up / i nput enabled pull - up / i nput enabled d mode input pin input enabled input enabled input enabled input enabled input enabled input ena bled e jtag select ed hi - z pull - up / i nput enabled pull - up / i nput enabled maintain previous state maintain previous state maintain previous state gpio selected setting disabled setting disabled setting disabled hi - z / i nternal input fixed at " 0 " f trace selected setting disabled setting disabled setting disabled maintain previous state maintain previous state trace output external interrupt enabled selected maintain previous state gpio selected , or resource other than above selected hi - z hi - z / i nput enabled hi - z / i nput enabled hi - z / i nternal input fixed at " 0 " d a t a s h e e t december 1 6 , 2014 , mb9a110a - ds706 - 00011 - 3v0 - e 61 confidential pin status type function group power - on reset or low - voltage detection state initx input state device internal reset state run mode or sleep mode state timer mode or stop mode state power supply unstable power supply stable power supply stable power supply stable - initx=0 initx=1 initx=1 initx=1 - - - - spl=0 spl=1 g trace selected setting disabled setting disabled setting disabled maintain previous state maintain previous s tate trace output gpio selected , or resource other than above selected hi - z hi - z / i nput enabled hi - z / i nput enabled hi - z / i nternal input fixed at " 0 " h external interrupt enabled selected setting disabled setting disabled setting disabled maintain pre vious state maintain previous state maintain previous state gpio selected , or resource other than above selected hi - z hi - z / i nput enabled hi - z / i nput enabled hi - z / i nternal input fixed at " 0 " i gpio selected , resource selected hi - z hi - z / i nput enabled hi - z / i nput enabled maintain previous state maintain previous state hi - z / i nternal input fixed at " 0 " j nmix selected setting disabled setting disabled setting disabled maintain previous state maintain previous state maintain previous state gpio select ed , or resource other than above selected hi - z hi - z / i nput enabled hi - z / i nput enabled hi - z / i nternal input fixed at " 0 " d a t a s h e e t 62 mb9a110a - ds706 - 00011 - 3 v0 - e, december 1 6 , 2014 confidential pin status type function group power - on reset or low - voltage detection state initx input state device internal reset state run mo de or sleep mode state timer mode or stop mode state power supply unstable power supply stable power supply stable power supply stable - initx=0 initx=1 initx=1 initx=1 - - - - spl=0 spl=1 k analog input selected hi - z hi - z / i nternal input fixed a t " 0 " / a nalog input enabled hi - z/ i nternal input fixed at " 0 " / a nalog input enabled hi - z/ i nternal input fixed at " 0 " / a nalog input enabled hi - z/ i nternal input fixed at " 0 " / a nalog input enabled hi - z/ i nternal input fixed at " 0 " / a nalog input enabled gp io selected , or resource other than above selected setting disabled setting disabled setting disabled maintain previous state maintain previous state hi - z / i nternal input fixed at " 0 " l external interrupt enabled selected setting disabled setting disabled setting disabled maintain previous state maintain previous state maintain previous state analog input selected hi - z hi - z / i nternal input fixed at " 0 " / a nalog input enabled hi - z/ i nternal input fixed at " 0 " / a nalog input enabled hi - z/ i nternal input fixe d at " 0 " / a nalog input enabled hi - z/ i nternal input fixed at " 0 " / a nalog input enabled hi - z/ i nternal input fixed at " 0 " / a nalog input enabled gpio selected , or resource other than above selected setting disabled setting disabled setting disabled maintai n previous state maintain previous state hi - z / i nternal input fixed at " 0 " m gpio selected setting disabled setting disabled setting disabled maintain previous state maintain previous state hi - z/ internal input fixed at " 0 " sub crystal oscillator input pin input enabled input enabled input enabled input enabled input enabled input enabled d a t a s h e e t december 1 6 , 2014 , mb9a110a - ds706 - 00011 - 3v0 - e 63 confidential pin status type function group power - on reset or low - voltage detection state initx input state device internal reset state run mode or sleep mode state timer mode o r stop mode state power supply unstable power supply stable power supply stable power supply stable - initx=0 initx=1 initx=1 initx=1 - - - - spl=0 spl=1 n gpio selected setting disabled setting disabled setting disabled maintain previous state m aintain previous state hi - z/ internal input fixed at " 0 " sub crystal oscillator output pin hi - z / internal input fixed at " 0 " / or input enable d hi - z / internal input fixed at " 0 " hi - z / internal input fixed at " 0 " maintain previous state maintain previous s tate/ hi - z at oscillation stop * 2 / internal input fixed at " 0 " maintain previous state/ hi - z at oscillation stop * 2 / internal input fixed at " 0 " o gpio pin hi - z hi - z/ input enabled hi - z/ input enabled maintain previous state maintain previous state hi - z/ in ternal input fixed at " 0 " p mode input pin input enabled input enabled input enabled input enabled input enabled input enabled gpio selected setting disabled setting disabled setting disabled maintain previous state maintain previous state hi - z/input en abled *1 : oscillation is stopped at sub timer mode , low - speed cr timer mode, and stop mode. *2 : oscillation is stopped at stop mode. d a t a s h e e t 64 mb9a110a - ds706 - 00011 - 3v0 - e, december 16 , 2014 confidential ? electrical characteristics 1. absolute maximum ratings parameter symbol rating unit remarks min max power supply voltage* 1 , * 2 v cc v ss - 0.5 v ss + 6.5 v analog power supply voltage * 1, * 3 av cc v ss - 0.5 v ss + 6.5 v analog reference volta ge * 1, * 3 avrh v ss - 0.5 v ss + 6.5 v input voltage* 1 v i v ss - 0.5 v cc + 0.5 ( ss - 0.5 v ss + 6.5 v 5v tolerant analog pin input voltage * 1 v ia v ss - 0.5 av cc + 0.5 ( 1 v o v ss - 0.5 v cc + 0.5 ( clamp - 2 +2 ma * 7 clamp total maximum current clam p ] +20 ma * 7 " l " level maximum output current* 4 i ol - 10 ma 4ma type 20 ma 12ma type 39 ma p80, p81 " l " level average output current* 5 i olav - 4 ma 4ma type 12 ma 12ma type 18.5 ma p80, p81 " l " level total maximum output current ol - 100 ma " l " level total average output current* 6 olav - 50 ma " h " level maximum output current* 4 i oh - - 10 ma 4ma type - 20 ma 12ma type - 39 ma p80, p81 " h " level average output current* 5 i ohav - - 4 ma 4ma type - 12 ma 12ma type - 20.5 ma p80, p81 " h " level total maximum output current oh - - 100 ma " h " level total average output current* 6 ohav - - 50 ma power consumption p d - 300 mw storage temperature t stg - 55 + 150 c *1 : these parameters are based on the condition that v ss = av ss = 0.0v . * 2 : vcc must not drop below v ss - 0.5v. * 3 : be careful not to exceed v cc + 0.5 v, for example, when the power is turned on. * 4 : the maximum output current is defined as the value of the peak current flowing through any o ne of the corresponding pins. * 5 : the average output current is defined as the average current value flowing through any one of the corresponding pins for a 100 ms period. * 6 : the total average output current is defined as the average current value flowi ng through all of corresponding pins for a 100ms. d a t a s h e e t december 16 , 2014 , mb9a110a - ds706 - 00011 - 3v0 - e 65 confi dential * 7 : ? see " ? list of pin functions " and " ? i/o circuit type " about +b input available pin. ? use within recommended operating conditions. ? use at dc voltage (current) the +b input . ? the +b signal should always be applied a limiting resistance placed between the +b signal and the device. ? the value of the limiting resistance should be set so that when the +b signal is applied the input current to the device pin does not exceed rated values, either instantaneously or for prolonged periods. ? note that when the device drive current is low, such as in the low - power consumpsion modes, the +b input potential may pass through the protective diode and increase the potential at the v cc and avcc pin, and this may affect other d evices. ? note that if a +b signal is input when the device power supply is off (not fixed at 0v), the power supply is provided from the pins, so that incomplete operation may result. ? the following is a r ecommended circuit example (i/o equivalent circuit ) . < warning > semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. do not exceed these ratin gs. r +b input (0v to 16v) protection diode p - ch v cc v cc limiting resistor n - ch av cc analog input digital input digital output d a t a s h e e t 66 mb9a110a - ds706 - 00011 - 3v0 - e, december 16 , 2014 confidential 2. recommended operating conditions ( vss = avss = 0.0v ) parameter symbol conditions value unit remarks min max power supply voltage vcc - 2.7 * 2 5.5 v analog power supply voltage avcc - 2.7 5.5 v avcc = vcc analog reference voltage avrh - 2.7 avcc v smoothing capacitor c s - 1 10 f for built - in regulator* 1 operating t emperature fpt - 100p - m23 fpt - 80p - m37 fpt - 64p - m38 fpt - 64p - m39 lcc - 64p - m24 bga - 112p - m04 ta - - 40 + 105 c fpt - 100p - m06 ta when mounted on four - layer pcb - 40 + 105 c when mounted on double - sided single - layer pcb - 40 + 105 c icc c pin" in " ? handling devices" for the connection of the smoothing capacitor. * 2 : in between less than the minimum power supply voltag e and low voltage reset/interrupt detection voltage or more, instruction execution and low voltage detection function by built - in high - speed cr(including main pll is used) or built - in low - speed cr is possible to operate only. < warning > the recommended ope rating conditions are required in order to ensure the normal operation of the semiconductor device. all of the device's electrical characteristics are warranted when the device is operated within these ranges. always use semiconductor devices within their recommended operating condition ranges. operation outside these ranges may adversely affect reliability and could result in device failure. no warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. u sers considering application outside the listed conditions are advised to contact their representatives beforehand. d a t a s h e e t december 16 , 2014 , mb9a110a - ds706 - 00011 - 3v0 - e 67 confi dential 3. dc characteristics ? current rating ( v cc = av cc = 2.7 v to 5.5v, vss = avss = 0v , ta = - 40 c to + 10 5 c ) parameter symbol pin name conditions value unit remarks typ * 3 max * 4 run mode current icc v cc pll run mode cpu : 40mhz, peripheral : 40mhz, flash 0wait frwtr.rwt = 00 fsyndn.sd = 000 *5 32 41 ma *1 cpu : 4 0mhz, peripheral : 40mhz, flash 3wait frwtr.rwt = 00 fsyndn.sd = 011 *5 21 28 ma *1 high - speed cr run mode cpu/ peripheral : 4mhz* 2 flash 0wait frwtr.rwt = 00 fsyndn.sd = 000 3.9 7.7 ma *1 sub ru n mode cpu/ peripheral : 32khz flash 0wait frwtr.rwt = 00 fsyndn.sd = 000 *6 0.15 3.2 ma *1 low - speed cr run mode cpu/ peripheral : 100khz flash 0wait frwt r.rwt = 00 fsyndn.sd = 000 0.2 3.3 ma *1 sleep mode current iccs pll sleep mode peripheral : 40mhz *5 10 15 ma *1 high - speed cr sleep mode peripheral : 4mhz* 2 1.2 4. 4 ma *1 sub sleep mode peripheral : 32khz *6 0.1 3.1 ma *1 low - speed cr sleep mode peripheral : 100khz 0.1 3.1 ma *1 *1 : when a l l ports are fixed. *2 : when setting it to 4mhz by trimming. * 3 : ta=+25c, v cc = 5.5 v * 4 : ta=+ 105 c, v cc =5.5v *5 : when using the crystal oscillator of 4 mhz(including the current consumption of the oscillation circuit ) * 6 : when using the crystal oscillator of 32 khz(incl uding the current consumption of the oscillation circuit ) d a t a s h e e t 68 mb9a110a - ds706 - 00011 - 3v0 - e, december 16 , 2014 confidential (vcc = avcc = 2.7v to 5.5v, vss = avss = 0v, ta = - 40 c to + 105 c ) parameter symbol pin name conditions value unit remarks typ * 2 max * 2 timer mode current i cct vcc main timer mode ta = + 25 c, when lvd is off * 3 2.5 3 m a *1 ta = + 105 c, when lvd is off * 3 - 6 ma *1 sub timer mode ta = + 25 c, when lvd is off * 4 60 230 - 3.1 ma *1 stop mode current i cch stop mode ta = + 25 c, when lvd is off 35 200 - 3 ma *1 *1 : when a l l ports are fixed. * 2 : v cc = 5.5v * 3 : when using the crystal oscillator of 4 mhz(including the current consumption of the oscillation circuit ) * 4 : when using the crystal oscillator of 32 khz(including the current consumption of the oscillation circuit ) low - v oltage d etection curre nt (v cc = 2.7v to 5.5v, v ss = 0v, ta = - 40c to + 105 c) parameter symbol pin name conditions value unit remarks typ max low - voltage detection circuit (lvd) power supply current i cclvd vcc at operation for interrupt vcc = 5.5v 4 7 at not detect flash memory current (v cc = 2.7v to 5.5v, v ss = 0v, ta = - 40c to + 105 c) parameter symbol pin name conditions value unit remarks typ max flash m emory w rite/ e rase current i ccflash vcc at write/erase 11.4 13.1 ma a/d converter current (v cc = av cc = 2.7v to 5.5v, v ss = av ss = avrl = 0v, ta = - 40c to + 105 c) parameter symbol pin name conditions value unit remarks typ m ax power supply current i ccad avcc at 1unit operation 0.57 0.72 ma at stop 0.06 20 ccavrh avrh at 1unit operation avrh=5.5v 1.1 1.96 ma at stop 0.06 4 d a t a s h e e t december 16 , 2014 , mb9a110a - ds706 - 00011 - 3v0 - e 69 confi dential ? pin characteristics (v cc = av cc = 2.7v to 5.5v, vss = avss = 0v , ta = - 40 c to + 10 5 c ) parameter symbol pin name conditions value unit remarks min typ max "h" level input voltage (hysteresis input) v ihs cmos hysteresis input pin, md0,1 - vcc 0.8 - vcc + 0.3 v 5v tolerant i/o pin - vcc 0.8 - vss + 5 .5 v " l " level input voltage (hysteresis input) v ils cmos hysteresis input pin, md0,1 - vss - 0.3 - vcc 0.2 v "h" level output voltage v oh 4ma type v cc oh = - 4ma vcc - 0.5 - vcc v v cc < 4.5 v i oh = - 2ma 12ma type v cc oh = - 12ma vcc - 0.5 - vcc v v cc < 4.5 v i oh = - 8ma p80, p81 v cc oh = - 20.5 ma vcc - 0.4 - vcc v v cc < 4.5 v i oh = - 13.0 ma "l" level output voltage v ol 4ma type v cc o l = 4ma vss - 0.4 v v cc < 4.5 v i o l = 2ma 12ma type v cc o l = 12ma vss - 0.4 v v cc < 4.5 v i o l = 8ma p80, p81 v cc o l = 18.5 ma vss - 0.4 v v cc < 4.5 v i ol = 10.5 ma input leak current i il - - - 5 - + 5 a pu pull - up pin v cc k in other than vcc, vss, avcc, avss, avrh - - 5 15 pf d a t a s h e e t 70 mb9a110a - ds706 - 00011 - 3v0 - e, december 16 , 2014 confidential 4. ac characteristics (1) main clock input characteristics ( v cc = 2.7v to 5.5v, vss = 0v , ta = - 40 c to + 10 5 c ) parameter symbol pin name conditions value unit remarks min max input frequency f ch x0 x1 vcc cylh v cc w h /t cylh p wl /t cylh 45 55 % when using external clock input clock ris ing time and fall ing time t cf t cr - - 5 ns when using external clock internal operating clock * 1 frequency f c m - - - 40 mhz master clock f cc - - - 40 mhz base clock (hclk/fclk) f cp0 - - - 40 mhz apb0 bus clock * 2 f cp1 - - - 40 mhz apb1 bus clock * 2 f cp 2 - - - 40 mhz apb2 bus clock * 2 internal operating clock * 1 cycle time t cycc - - 25 - ns base clock (hclk/fclk) t cycp0 - - 25 - ns apb0 bus clock * 2 t cycp1 - - 25 - ns apb1 bus clock * 2 t cycp2 - - 25 - ns apb2 bus clock * 2 *1 : for more information about each internal operating clock , see " c hapter 2 - 1 : clock " in " fm3 family peripheral manual ". *2 : for about each apb bus which each peripheral is connected to , see " ? block diagram" in this data sheet. x0 d a t a s h e e t december 16 , 2014 , mb9a110a - ds706 - 00011 - 3v0 - e 71 confi dential (2) sub clock input characteristics ( v cc = 2.7v to 5.5v, vss = 0v , ta = - 40 c to + 10 5 c ) parameter symbol pin name conditions value unit remarks min typ max inp ut frequency f cl x0a x1a - - 32.768 - khz when crystal oscillator is connected - 32 - 100 khz when using external clock input clock cycle t cyll - 10 - 31.25 wh /t cyll p wl /t cyll 45 - 55 % when using external clock (3) built - in cr oscillation characteristics ? buil t - in hi gh - speed cr ( v cc = 2.7v to 5.5v, vss = 0v , ta = - 40 c to + 10 5 c ) parameter symbol conditions value unit remarks min typ max clock frequency f crh ta = + 25 c 3.9 6 4 4.0 4 mhz when trimming * 1 ta = 0 c to + 70 c 3.84 4 4.16 ta = - 40 c to + 105 c 3.8 4 4.2 ta = - 40 c to + 105 c 3 4 5 when not trimming f requency stability time t crwt - - - 90 2 *1 : in the case of using the values in cr trimming area of flash memory at shipment for frequency trimming. *2 : f requency stable time is time to stable of the frequency of the high - speed cr . clock after the trim value is set. after setting the tri m value, the period when the frequency stability time passes can use the high - speed cr clock as a source clock. ? built - in low - speed cr (vcc = 2.7v t o 5.5v, vss = 0v , ta = - 40 c to + 10 5 c ) parameter symbol conditions value unit remarks min typ max clock frequency f crl - 50 100 150 k hz x0 a d a t a s h e e t 72 mb9a110a - ds706 - 00011 - 3v0 - e, december 16 , 2014 confidential (4 - 1 ) operating conditions of main pll ( in the case o f using m ain clock for input clock of pll) ( v cc = 2.7 v to 5.5v, vss = 0v , ta = - 40 c to + 10 5 c ) parameter symbol value unit remarks min typ max pll oscillation stabilization wait time (lock up time)* 1 t lock 100 - - plli 4 - 16 mh z pll multiple rate - 13 - 75 multiple pll macro oscillation clock frequency f pllo 200 - 300 mh z main pll clock frequency* 2 f clkpll - - 40 mh z *1 : time from when the pll starts operating until the oscillation stabilizes. *2 : for more information about main pll clock (clkpll), see "c h apter 2 - 1 : clock" in "fm3 family peripheral manual". (4 - 2) operating conditions of main pll (in the case of using the built - in high speed cr for the input clock of the main pll ) (vcc = 2.7v to 5.5v, vss = 0v, ta = - 40 c to + 105 c ) parameter symbol value unit remarks min typ max pll oscillation stabilization wait time (lock up time)* 1 t lock 100 - - plli 3.8 4 4.2 mh z pll multiple rate - 50 - 7 1 multiple pll macro oscillation clock frequency f pllo 19 0 - 300 mh z main pll clock frequency* 2 f clkpll - - 40 mh z * 1 : time from when the pll starts operating until the oscillation stabilizes. *2 : for more information about main pll clock (clkpll), see "c hapter 2 - 1 : clock" in "fm3 family peripheral manual". when setting pll multiple rate, please take the accuracy of the built - in high - speed cr clock into account and prevent the master clock from exceeding the maximum frequency . k divider pll input clock main pll pll macro osc illation clock m divider main pll clock (clkpll) n divider main pll connection high - speed cr clock (clkhc) main clock (clkmo) d a t a s h e e t december 16 , 2014 , mb9a110a - ds706 - 00011 - 3v0 - e 73 confi dential (5) reset input characteristics ( v cc = 2.7v to 5.5v, vss = 0v , ta = - 40 c to + 10 5 c ) parameter symbol pin name conditions value unit remarks min max reset input time t initx initx - 500 - ns (6) power - on reset timin g ( v cc = 2.7v to 5.5v, vss = 0v , ta = - 40 c to + 10 5 c ) parameter symbol pin name value unit remarks min max power supply rising time tr vcc 0 - ms power supply shut down time toff 1 - ms time until releasing power - on reset tprt 0.446 0.744 m s glossary ? vcc_minimum : minimum v cc of recommended operating conditions ? vd h _minimum : minimum release voltage of low - v oltage detection reset . see " 8 . low - v oltage detection characteristics " 0 . 2 v v d h _ m i n i m u m v c c _ m i n i m u m t p r t i n t e r n a l r s t v c c c p u o p e r a t i o n s t a r t r s t a c t i v e r e l e a s e t r 0 . 2 v 0 . 2 v t o f f d a t a s h e e t 74 mb9a110a - ds706 - 00011 - 3v0 - e, december 16 , 2014 confidential (7) external bus timing ? external bus clock output characteristics (vcc = 2.7v to 5.5v, vss = 0v , ta = - 40 c to + 105 c ) parameter symbol pin name conditions value unit min max o ut put frequency t cycle mclkout vcc ? external bus signal input/output charac teristics (vcc = 2.7v to 5.5v, vss = 0v , ta = - 40 c to + 105 c ) parameter symbol conditions value unit remarks signal input c haracteristics v ih - 0.8 v cc v v il 0.2 v cc v signal output c haracteristics v oh 0.8 v cc v v ol 0.2 v cc v mclkout input signal output signal v ih v il v il v ih v oh v ol v ol v oh d a t a s h e e t december 16 , 2014 , mb9a110a - ds706 - 00011 - 3v0 - e 75 confi dential ? separate bus access asynchronous sram mode (vcc = 2.7v to 5.5v, vss = 0v , ta = - 40 c to + 105 c ) parameter symbol pin name conditions value unit min max m oe x min pulse width t oew moex vcc csl C av mcsx[7:0] mad[24:0] vcc oeh - ax moex mad[24:0] vcc cs l - oe l moex mcsx[7:0] vcc oeh - c sh vcc cs l - r dqml mcsx mdqm [1:0] vcc ds - oe moex madata[15:0] vcc dh - oe moex madata[15:0] vcc wew mwex vcc weh - ax mwex mad[24:0] vcc csl - wel mwex mcsx[7:0] vcc weh - csh vcc cs l - w dqml mcsx mdqm[1:0] vcc cs l - dv mcsx madata[15:0] vcc 4.5v weh - dx mwex madata[15:0] vcc 4.5v l = 30pf (m = 0 to 15, n = 1 to 16) . d a t a s h e e t 76 mb9a110a - ds706 - 00011 - 3v0 - e, december 16 , 2014 confidential mclk mcsx[7:0] mad[24:0] mdqm[1:0] mwex madata[15:0] moex i n v a l i d a d d r e s s t c s l - o e l t c s l - a v r d a d d r e s s w d t d h - o e t d s - o e t w e h - d x t o e w t o e h - a x t o e h - c s h t w e w t c y c l e t c s l - w e l t c s l - a v t w e h - c s h t w e h - a x t c s l - w d q m l t c s l - r d q m l t c s l - d v d a t a s h e e t december 16 , 2014 , mb9a110a - ds706 - 00011 - 3v0 - e 77 confi dential ? separate bus access synchronous sram mode (vcc = 2.7v to 5.5v, vss = 0v , ta = - 40 c to + 105 c ) parameter symbol pin name conditions value u nit min max address delay time t av mclk mad[24:0] vcc csl mclk mcsx[7:0] vcc cs h vcc rel mclk moex vcc reh vcc ds mclk madata[15:0] vcc dh mclk madata[15:0] vcc wel mclk mwex vcc we h vcc dqml mclk mdqm[1:0] vcc dqmh vcc data output time t ods mclk, madata[15:0] v cc 4.5v cc < 4.5v mclk+24 mclk od mclk madata[15:0] vcc 4.5v l = 3 0pf. mclk mcsx[7:0] mad[24:0] mdqm[1:0] mwex madata[15:0] moex i n v a l i d t d q m l t r e h a d d r e s s t c s l t a v t r e l r d a d d r e s s w d t d q m h t w e h t w e l t d h t d s t o d t a v t c s h t c y c l e t d q m l t d q m h t o d s d a t a s h e e t 78 mb9a110a - ds706 - 00011 - 3v0 - e, december 16 , 2014 confidential ? multiplexed bus access asynchronous sram mode (vcc = 2.7v to 5.5v, vss = 0v , ta = - 40 c to + 105 c ) parameter symbol pin name conditions value unit min max multiplexed address delay time t a le - chmadv male madata[15:0] vcc c hma dh vcc l = 30pf (m = 0 to 15, n = 1 to 16) . mclk mcsx[7:0] male moex mwex mad ata[15:0] mad [24:0] mdqm [1:0] d a t a s h e e t december 16 , 2014 , mb9a110a - ds706 - 00011 - 3v0 - e 79 confi dential ? mult iplexed bus access synchronous sram mode (vcc = 2.7v to 5.5v, vss = 0v , ta = - 40 c to + 105 c ) parameter symbol pin name conditions value unit remarks min max male delay time t chal mclk ale vcc chah vcc chmadv m clk madata[15:0] vcc od ns vcc < 4.5v mclk chmad x vcc od ns vcc < 4.5v note: when the exter nal load capacitance c l = 30pf . mclk mcsx[7:0] male moex mwex madata[15:0] mad [24:0] mdqm [1:0] d a t a s h e e t 80 mb9a110a - ds706 - 00011 - 3v0 - e, december 16 , 2014 confidential ? external ready input timing (vcc = 2.7v to 5.5v, vss = 0v , ta = - 40 c to + 105 c ) parameter symbol pin name conditions value unit remarks min max mclk rdyi mclk mrdy vcc ? when rdy is input ? when rdy is release d mclk original moex mwex mrdy mclk extended moex mwex mrdy over 2cycles t rdyi 2 cycles t rdyi 0.5vcc d a t a s h e e t december 16 , 2014 , mb9a110a - ds706 - 00011 - 3v0 - e 81 confi dential (8) base timer input timing ? timer input timing ( vcc = 2.7v to 5.5v, vss = 0v , ta = - 40 c to + 10 5 c ) parameter symbol pin name conditions value unit remarks min max input pulse width t tiwh t tiwl tioan /tiobn (when using as eck,tin ) - 2 t cycp - ns ? trigger input timing ( vcc = 2.7v to 5.5v, vss = 0v , ta = - 40 c to + 10 5 c ) parameter symbol pin name conditions value unit remarks min max input pulse width t trgh t trgl tioan/tiobn (when using as tgin ) - 2 t cycp - ns note: t cycp indicates the apb bus clock cycle time. about the apb bus number which th e base timer is connected to, see " ? block diagram" in this data sheet. tgin eck tin t tiwh v ihs v ihs v ils v ils t tiw l t trgh v ihs v ihs v ils v ils t trg l d a t a s h e e t 82 mb9a110a - ds706 - 00011 - 3v0 - e, december 16 , 2014 confidential (9) csio/ uart timing ? csio (spi = 0, scinv = 0 ) (vcc = 2.7v to 5.5v, vss = 0v , ta = - 40 c to + 10 5 c ) parameter symbol pin name conditions v cc < 4.5v vcc 4.5v unit min max min max serial clock cycle time t scyc sckx master mode 4tcycp - 4tcycp - ns sck slovi sckx sotx - 30 + 30 - 20 + 20 ns sin ivshi sckx sinx 50 - 30 - ns sck shixi sckx sinx 0 - 0 - n s serial clock "l" pulse width t slsh sckx slave mode 2tcycp - 10 - 2tcycp - 10 - ns serial clock "h" pulse width t shsl sckx tcycp + 10 - tcycp + 10 - ns sck slove sckx sotx - 50 - 30 ns sin ivshe sckx sinx 10 - 10 - ns sck shixe sckx sinx 20 - 20 - ns sck fall ing time tf sckx - 5 - 5 ns sck ris ing time tr sckx - 5 - 5 ns notes: ? the above characteristics apply to clk synchronous mode. ? t cycp indicates the apb bus clock cycle time. about the apb bus number which multi - function serial is connected to , see " ? ? these characteristics only guarantee the same relocate port number. for example, the combination of sc kx_0 and sotx_1 is not guaranteed. ? w hen the external load capacitance c l = 30pf. d a t a s h e e t december 16 , 2014 , mb9a110a - ds706 - 00011 - 3v0 - e 83 confi dential master mode slave mode sck sot sin sck sot sin t scyc v oh v oh v ol v ol v ol v ih v il v ih v il t slovi t ivshi t shixi t slsh t shsl v ih t f tr v ih v oh v ih v il v il v ol v ih v il v ih v il t slove t ivshe t shixe d a t a s h e e t 84 mb9a110a - ds706 - 00011 - 3v0 - e, december 16 , 2014 confidential ? csio ( spi = 0, scinv = 1 ) (vcc = 2.7v to 5.5v, vss = 0v , ta = - 40 c to + 10 5 c ) parameter symbol pin name conditions vcc < 4.5v vcc 4.5v unit min max min max serial clock cycle time t scyc sckx master mode 4tcycp - 4tcycp - ns sck shovi sckx sotx - 30 + 30 - 20 + 20 ns sin ivsli sckx sinx 50 - 30 - ns s ck slixi sckx sinx 0 - 0 - ns serial clock " l" pulse width t slsh sckx slave mode 2tcycp - 10 - 2tcycp - 10 - ns serial clock " h" pulse width t shsl sckx tcycp + 10 - tcycp + 10 - ns sck shove sckx sotx - 50 - 30 ns sin ivsle sckx sinx 10 - 10 - ns sck slixe sckx sinx 20 - 20 - ns sck fall ing time tf sckx - 5 - 5 ns sck ris ing time tr sckx - 5 - 5 ns notes: ? the above characteristics appl y to clk synchronous mode. ? t cycp indicates the apb bus clock cycle time. about the apb bus number which multi - function serial is connected to, see " ? ? these characteristics only guarantee the same relocate port numb er. for example, the combination of sc kx_0 and sotx_1 is not guaranteed. ? when the external load capacitance c l = 30pf. d a t a s h e e t december 16 , 2014 , mb9a110a - ds706 - 00011 - 3v0 - e 85 confi dential ma ster mode slave mode sck sot sin sck sot sin t scyc v oh v oh v oh v ol v ol v ih v il v ih v il t shovi t ivsli t slixi t shsl t slsh v ih tf tr v ih v oh v il v il v il v ol v ih v il v ih v il t shove t ivsle t slixe d a t a s h e e t 86 mb9a110a - ds706 - 00011 - 3v0 - e, december 16 , 2014 confidential ? csio ( spi = 1, scinv = 0 ) (vcc = 2.7v to 5.5v, vss = 0v , ta = - 40 c to + 10 5 c ) parameter symbol pin name conditions vcc < 4.5v vcc 4.5v unit min max min max serial clock cycle time t scyc sckx master mode 4tcycp - 4tcycp - ns sck shovi sckx sotx - 30 + 30 - 20 + 20 ns sin ivsli sckx sinx 50 - 30 - ns sck slixi sckx sinx 0 - 0 - ns sot sovli sckx sotx 2tcycp - 30 - 2tcycp - 30 - ns serial clock " l" pulse width t slsh sckx slave mode 2tcycp - 10 - 2tcycp - 10 - ns serial clock " h" pulse width t shsl sckx tcycp + 10 - tcycp + 10 - ns sck shove sckx s ot x - 50 - 30 ns sin ivsle sckx sinx 10 - 10 - ns sck slixe sckx sinx 20 - 20 - ns sck fall ing time tf sckx - 5 - 5 ns sck ris ing time tr sckx - 5 - 5 ns notes: ? the above characteristics apply to clk synchronous mode. ? t cycp indicates the apb bus clock cycle time. about the apb bus number which multi - function serial is connected to , see " ? ? these characteristics only guarantee the same relocate port number. for example, the combination of sc kx_0 and sotx_1 is not guaranteed. ? w hen the external load capacitance c l = 30pf. d a t a s h e e t december 16 , 2014 , mb9a110a - ds706 - 00011 - 3v0 - e 87 confi dential master mode slave mode *: changes when writing to tdr register sck sot sin sck sot sin t sovli t scyc t shovi v ol v ol v oh v oh v ol v oh v ol v ih v il v ih v il t ivsli t slixi tf tr t slsh t shsl t shove v il v il v ih v ih v ih v oh * v ol v oh v ol v ih v il v ih v il t ivsle t slixe d a t a s h e e t 88 mb9a110a - ds706 - 00011 - 3v0 - e, december 16 , 2014 confidential ? csio ( spi = 1, scinv = 1 ) (vcc = 2.7v to 5.5v, vss = 0v , ta = - 40 c to + 10 5 c ) parameter symbol pin name conditions vcc < 4.5v vcc 4.5v unit min max min max serial clock cycle time t scyc sckx master mode 4tcycp - 4tcycp - ns sck slovi sckx sotx - 30 + 30 - 20 + 20 ns sin ivshi sckx sinx 50 - 30 - ns sck shixi sckx sinx 0 - 0 - ns sot sovhi sckx sotx 2tcycp - 30 - 2tcycp - 30 - ns serial clock "l" pulse width t slsh sckx slave mode 2tcycp - 10 - 2tcycp - 10 - ns serial clock "h" pulse width t shsl sckx tcycp + 10 - tcycp + 10 - ns sck slove sckx s ot x - 50 - 30 ns sin ivshe sckx sinx 10 - 10 - ns sck shixe sckx sinx 20 - 20 - ns sck fall ing time tf sckx - 5 - 5 ns sck r is ing time tr sckx - 5 - 5 ns notes: ? the above characteristics apply to clk synchronous mode. ? t cycp indicates the apb bus clock cycle time. about the apb bus number which multi - function serial is connected to, see " ? ? these characteristics only guarantee the same relocate port number. for example, the combination of sc kx_0 and sotx_1 is not guaranteed. ? when the external load capacitance c l = 30pf. d a t a s h e e t december 16 , 2014 , mb9a110a - ds706 - 00011 - 3v0 - e 89 confi dential master mode slave mode ? uart e xternal clock in put ( ext = 1 ) (vcc = 2.7v to 5.5v, vss = 0v , ta = - 40 c to + 10 5 c ) parameter symbol conditions min max unit remarks serial clock " l" pulse width t slsh c l = 30pf tcycp + 10 - ns serial clock " h" pulse width t shsl tcycp + 10 - ns sck fall ing time tf - 5 ns sck ris ing time tr - 5 ns sck sot sin sck sot sin s ck t scyc t slovi v ol v oh v oh v oh v ol v oh v ol v ih v il v ih v il t ivshi t shixi t sovhi t shsl tr t slsh tf t slove v il v il v il v ih v ih v ih v oh v ol v oh v ol v ih v il v ih v il t ivshe t shixe t shsl v i l v i l v i l v ih v ih v ih tr tf t slsh d a t a s h e e t 90 mb9a110a - ds706 - 00011 - 3v0 - e, december 16 , 2014 confidential (10) external input timing ( vcc = 2.7v to 5.5v, vss = 0v , ta = - 40 c to + 10 5 c ) parameter symbol pin name con ditio ns value unit remarks min max input pulse width t inh t inl adtg - 2 t cycp * - ns a/d converter trigger input frck x free - run timer input clock icxx input capture dttixx - 2 t cycp * - ns wave form generator int xx , nmi x except timer mode, stop mode 2 t cycp + 100 * - ns external interrupt nmi timer mode, stop mode 500 - ns * : t cycp indicates the apb bus clock cycle time . about the apb bus number which the a/d conver ter, multi - function timer, external interrupt are connected to, see " ? block diagram" in this data sheet. d a t a s h e e t december 16 , 2014 , mb9a110a - ds706 - 00011 - 3v0 - e 91 confi dential (11) quadrature position/revol ution counter timing (vcc = 2.7v to 5.5v, vss = 0v , ta = - 40 c to + 10 5 c ) parameter symbol conditions value unit min max ain pin "h" width t ahl - 2 t cycp * - ns ain pin "l" width t all - bin pin "h" width t bhl - bin pin "l" width t bll - bin rise time from ain pin "h" level t aubu pc_mode2 or pc_ m ode3 ain fall time from bin pin "h" level t buad pc_mode2 or pc_mode3 bin fall time from ain pin "l" level t adbd pc_mode2 or pc_mode3 ain rise time from bin pin "l" level t bdau pc_mo de2 or pc_mode3 ain rise time from bin pin "h" level t buau pc_mode2 or pc_mode3 bin fall time from ain pin "h" level t aubd pc_mode2 or pc_mode3 ain fall time from bin pin "l" level t bdad pc_mode2 or pc_mode3 bin rise time from ain pin " l" level t adbu pc_mode2 or pc_mode3 zin pin "h" width t zhl qcr:cgsc = "0" zin pin "l" width t zll qcr:cgsc = "0" ain/bin rise and fall time from determined zin level t zabe qcr:cgsc = "1" determine d zin level from ain/bin rise and fall time t abez qcr:cgsc = "1" * : t cycp indicates the apb bus clock cycle time . about the apb bus number which quadrature position/revolution counter is connected to, see " ? block diagram" in this data sheet. ain bin t aubu t buad t adbd t bdau t ahl t all t bhl t bll d a t a s h e e t 92 mb9a110a - ds706 - 00011 - 3v0 - e, december 16 , 2014 confidential zin zin ain/bin bin t buau t aubd t bdad t adbu t bhl t bll t ahl t all ain d a t a s h e e t december 16 , 2014 , mb9a110a - ds706 - 00011 - 3v0 - e 93 confi dential (12 ) i 2 c timing ( vcc = 2.7v to 5.5v, vss = 0v , ta = - 40 c to + 10 5 c ) parameter symbol conditions standard - mode fast - mode unit remarks min max min max scl clock frequency f scl c l = 30pf , r = (vp/i ol )* 1 0 100 0 400 khz ( repeated ) start condition hold time sda hdsta 4.0 - 0.6 - low 4.7 - 1.3 - high 4.0 - 0.6 - susta 4.7 - 0.6 - hddat 0 3.45* 2 0 0.9* 3 sudat 250 - 100 - ns stop conditio n setup time scl susto 4.0 - 0.6 - buf 4.7 - 1.3 - sp - 2 t cycp * 4 - 2 t cycp * 4 - ns *1 : r and c represent the pull - up resistance and load capacitance of th e scl and sda lines, respectively. vp indicates the power supply voltage of the pull - up resistance and i ol indicates v ol guaranteed current. *2 : the maximum t hddat must satisfy that it doesn't extend at least "l" period (t low ) of device's scl signal. *3 : fast - mode i 2 c bus device can be used on s tandard - mode i 2 c bus system as long as the device satisfies the requirement of "t sudat 250 ns". *4 : t cycp is the apb bus clock cycle time. about the apb bus number that i2c is connected to, see " ? block diagram" in this data sheet. to use standard - mode, set the apb bus clock at 2 mhz or more. to use fast - mode, set the apb bus clock at 8 mhz or more. sda s cl d a t a s h e e t 94 mb9a110a - ds706 - 00011 - 3v0 - e, december 16 , 2014 confidential (13 ) etm timing ( vcc = 2.7v to 5.5v, vss = 0v , ta = - 40 c to + 10 5 c ) parameter symbol pin name con ditio ns val u e unit remarks min m ax data hold t etmh traceclk traced[3:0] vcc trace traceclk vcc trace vcc l = 30pf . hclk traceclk traced[3:0] d a t a s h e e t december 16 , 2014 , mb9a110a - ds706 - 00011 - 3v0 - e 95 confi dential (14 ) jtag timing (vcc = 2.7v to 5.5v, vss = 0v , ta = - 40 c to + 10 5 c ) parameter symbol pin name conditions value unit remarks min max tms, tdi setup time t jtags tck tms,tdi vcc jtagh tck tms,tdi vcc jtagd tck tdo vcc l = 30pf . tck tms/ tdi tdo d a t a s h e e t 96 mb9a110a - ds706 - 00011 - 3v0 - e, december 16 , 2014 confidential 5. 12 - bit a/d converter ? electrical c haracteristics for the a/d c onverter (vcc = avcc = 2.7v to 5.5v, vss = avss = 0v , ta = - 40 c to + 105 c ) parameter symbol pin name value unit remarks min typ max res olution - - - - 12 bit integral nonlinearity - - - 1.7 4.5 lsb avrh = 2.7v to 5.5v differential nonlinearity - - - 1.7 2.5 lsb zero transition voltage v zt an xx - 8 15 mv full - scale transition voltage v fst an xx - avrh 8 avrh 15 mv conversion time - - 1.0* 1 - - avcc 4.5v 1 avcc < 4.5v sampling time ts - *2 - - ns avcc 4.5v 3 tcck - 50 - 2000 ns state transition time to operation permission tstt - - - 1.0 ain - - - 12.9 pf analog input resistor r ain - - - 2 k avcc 4.5v avcc 4.5v, hclk= 40 mhz sampling time: 3 00n s, compare time: 700 ns avcc < 4.5v, hclk= 40 mhz sampling time: 500 ns, compare time: 700 ns ensure that it satis fies the value of the sampling time (ts) and compare clock cycle (tcck) . for setting of the sampling time and com p are clock cycle, see "c hapter 1 - 1 : a/d converter" in "fm3 family peripheral manual analog macro part " . the a/d converter register is set at apb bus clock timing. the s ampling clock and compare clock are set at base clock (hclk). about the apb bus number which the a/d converter is connected to, see " ? block diagram" in this data sheet. *2 : a necessary sampling time changes by external imped ance. ensure that it s et the sampling time to satisfy (equation 1) *3 : the c ompare time ( tc ) is the value of (equation 2) d a t a s h e e t december 16 , 2014 , mb9a110a - ds706 - 00011 - 3v0 - e 97 confi dential ( equation 1 ) ts (r ain + rext) c ain 9 ts : sampling time r ain : input resist or of a/d = 2 k 4.5 av cc 5.5 input resist or of a/d = 3.8 k 2.7 av cc < 4.5 c ain : input capacity of a/d = 1 2.9 pf 2.7 a v cc 5.5 rext : output impedance of external circuit ( equation 2 ) tc = tcck 14 tc : compare time tcck : compare clock cycle rext r ain c ain analog signal source an xx analog input pin c omparator d a t a s h e e t 98 mb9a110a - ds706 - 00011 - 3v0 - e, december 16 , 2014 confidential ? definition of 1 2 - bit a/d converter terms ? resolution : analog variation that is recognized by an a/d converter. ? integral nonl in earity : deviation of the line between the zero - transition point (0b000000000000 0b000000000001) and the full - scale transition point (0b111111111110 0b111111111111) from the actual conversion characteristics. ? differential non linearity : deviation from the ideal value of the input voltage that is required to change the output code by 1 lsb. integral nonlinearity of digital output n = v nt - {1lsb (n - 1) + v z t } [lsb] 1lsb diff erential nonlinearity of digital output n = v (n + 1) t - v nt - 1 [lsb] 1lsb 1lsb = v fst C z t 4094 n : a/d converter digital output value. v z t : voltage at which the digital output changes from 0x000 to 0x001. v fst : voltage at which the digital o utput changes from 0xffe to 0xfff. v nt : voltage at which the digital output changes from 0x(n ? 1) to 0xn. integral nonl inearity differential non linearity digital output digital output actual conversion characteristics actual conversion characteristics ideal characteristics (actually - measured value) actual conversion characteristics actual conversion characteristics (actually - measured value) (actually - measured value) ideal characteristics (actually - measured value) analog input analog input (actually - measured value) 0x001 0x002 0x003 0x004 0x f fd 0x f fe 0x f ff av ss avrh av ss avrh 0x(n - 2) 0x(n - 1) 0x(n+1) 0xn {1 lsb(n - 1) + v zt } v nt v fst v zt v nt v (n+1)t d a t a s h e e t december 16 , 2014 , mb9a110a - ds706 - 00011 - 3v0 - e 99 confi dential 6. low - voltage detection characteristics ? low - voltage detection reset ( ta = - 40 c to + 10 5 c ) parameter symbol conditions value unit remarks min typ max detected voltage vdl - 2.25 2.45 2.6 5 v when voltage drops released voltage vdh - 2.3 0 2.50 2.70 v when voltage rises ? interrupt of low - voltage detection ( ta = - 40 c to + 10 5 c ) parameter symbol conditions value unit remarks min typ max detected voltage v dl svhi = 0000 2.5 8 2.8 3.02 v when voltage drops released voltage vdh 2.6 7 2.9 3.13 v when voltage rises detected voltage vdl svhi = 0001 2.76 3.0 3.24 v when voltage drops released voltage vdh 2.85 3.1 3.34 v when voltage rises detected voltage vdl svhi = 0010 2.94 3.2 3.45 v when voltage drops released voltage vdh 3.0 4 3.3 3.56 v when voltage rises detected voltage vdl svhi = 0011 3.31 3.6 3.88 v when voltage drops released voltage vdh 3.40 3.7 3.99 v when voltage rises detected voltage vdl s vhi = 0100 3.40 3.7 3.99 v when voltage drops released voltage vdh 3. 50 3.8 4.10 v when voltage rises detected voltage vdl svhi = 0111 3.68 4.0 4.32 v when voltage drops released voltage vdh 3.77 4.1 4.42 v when voltage rises detected voltage vdl svh i = 1000 3.77 4.1 4.42 v when voltage drops released voltage vdh 3.86 4.2 4.53 v when voltage rises detected voltage vdl svhi = 1001 3.86 4.2 4. 53 v when voltage drops released voltage vdh 3.9 6 4.3 4.64 v when voltage rises lvd stabilization wait tim e t lvdw - - - 2240 tcycp * cycp indicates the apb2 bus clock cycle time. d a t a s h e e t 100 mb9a110a - ds706 - 00011 - 3v0 - e, december 16 , 2014 confidential 7. flash memory write/erase characteristics (1) write / erase time ( vcc = 2.7v to 5.5v , ta = - 40 c to + 10 5 c ) parameter value unit remarks typ * max * sector erase time large sector 0. 7 3.7 s in cludes write time prior to internal erase small sector 0.3 1.1 half word (16 bit) write time 12 384 (2) erase/write cycles and data hold time erase/write cycles (cycle) data hold time (year ) remarks 1,000 20 * 10,000 10 * 100,000 5 * * : at average + 85 ? c d a t a s h e e t december 16 , 2014 , mb9a110a - ds706 - 00011 - 3v0 - e 101 confi dential 8. return time from low - power consumption mode (1 ) return f actor: interrupt the return time from low - power consumption mode is indicated as follows. it is from receiving the return factor to starting the program ope ration. ? return c ount t ime ( v cc = 2.7v to 5.5v , ta = - 40 c to + 105 c ) parameter symbol value unit remarks typ max* sleep mode ticnt t cycc ns high - speed cr timer mode, main timer mode, pll timer mode 40 80 ? operation example of return from l ow - p ower consumption mode (by external interrupt*) * : external interrup t is set to detecting fall edge. e x t . i n t t i c n t i n t e r r u p t f a c t o r a c c e p t c p u o p e r a t i o n s t a r t a c t i v e i n t e r r u p t f a c t o r c l e a r b y c p u d a t a s h e e t 102 mb9a110a - ds706 - 00011 - 3v0 - e, december 16 , 2014 confidential ? operation example of return from low - power consumption mode (by internal resource interrupt*) * : internal resource interrupt is not included in return factor by the kind of low - power consumpt ion mode. notes: ? the return factor is different in each l ow - p ower consumption modes. see "c hapter 6 : low power consumption mode" and "operations of standby modes" in fm3 family peripheral manual about the return factor from l ow - p ower consumption mo de. ? when interrupt recoveries, the operation mode that cpu recoveries depends on the state before the low - power consumption mode transition. see "chapter 6 : low power consumption mode" in "fm3 family peripheral manual". i n t e r n a l r e s o u r c e i n t t i c n t i n t e r r u p t f a c t o r a c c e p t c p u o p e r a t i o n s t a r t a c t i v e i n t e r r u p t f a c t o r c l e a r b y c p u d a t a s h e e t december 16 , 2014 , mb9a110a - ds706 - 00011 - 3v0 - e 103 confi dential (2) return f actor: reset the return time from low - power consumption mode is indicated as follows. it is from releasing reset to starting the program operation. ? return c ount t ime ( v cc = 2.7v to 5.5v , ta = - 40 c to + 105 c ) parameter symbol value unit remarks typ max* sleep mode trcnt 308 444 ? operation e xample of return from l ow - p ower consumption mode (by initx) i n i t x t r c n t i n t e r n a l r s t c p u o p e r a t i o n s t a r t r s t a c t i v e r e l e a s e d a t a s h e e t 104 mb9a110a - ds706 - 00011 - 3v0 - e, december 16 , 2014 confidential ? operation example of return from low power consumption mode (by internal resource reset*) *: internal resource reset is not includ ed in return factor by the kind of low - power consumption mode. notes: ? the return factor is different in each low - power consumption modes. see "c hapter 6 : low power consumption mode" and "operations of standby modes" in fm3 family peripheral manual. ? when interrupt recoveries, the operation mode that cpu recoveries depends on the state before the low - power consumption mode transition. see "chapter 6 : low power consumption mode" in "fm3 family peripheral manual". ? the time during the power - on reset/ low - voltage detection reset is excluded. see "(6) power - on reset timing in 4. ac characteristics in ? when in recovery from reset, cpu changes t o the high - speed cr run mode. when using the main clock or the pll clock, it is necessary to add the main clock oscillation stabilization wait time or the main pll clock stabilization wait time. ? the internal resource reset means the watchdog reset and th e csv reset. i n t e r n a l r e s o u r c e r s t t r c n t i n t e r n a l r s t c p u o p e r a t i o n s t a r t r s t a c t i v e r e l e a s e d a t a s h e e t december 1 6 , 2014 , mb9a110a - ds706 - 00011 - 3v0 - e 105 confidential ? ordering information part number on - chip flash memory on - chip sram package packing MB9AF111LApmc1 - g - jne2 64kbyte 16kbyte plastic ? lqfp (0.5mm pitch), 64 - pin ( fpt - 64p - m38) tray mb9af112lapmc1 - g - jne2 128kbyte 16kbyte mb9af114lapmc1 - g - jne2 256kbyte 32kbyte MB9AF111LApmc - g - jne2 64kbyte 16kbyte plastic ? lqfp (0.65mm pitch), 64 - pin ( fpt - 64p - m39) mb9af112lapmc - g - jne2 128kbyte 16kbyte mb9af114lapmc - g - jne2 256kbyte 32kbyte MB9AF111LAqn - g - ave2 64kbyte 16kbyte plastic ? qfn (0.5mm pitch), 64 - pin (lcc - 64p - m24) mb9af112laqn - g - ave2 128kbyte 16kbyte mb9af114laqn - g - ave2 256kbyte 32kbyte mb9af111mapmc - g - jne2 64kbyte 16kbyte plastic ? lqfp (0.5mm pitch), 80 - pin ( fpt - 80p - m37) mb9af112mapmc - g - jne2 128kbyte 16kbyte mb9af114mapmc - g - jne2 256kbyte 32kbyte mb9af115mapmc - g - jne2 384kbyte 32kbyte mb9af116mapmc - g - jne2 512kbyte 32kbyte mb9af111napmc - g - jne2 64kbyte 16kbyte plastic ? lqfp (0.5mm pitch), 100 - pin ( fpt - 100p - m23) mb9af112napmc - g - jne2 128kbyte 16kbyte mb9af114napmc - g - j ne2 256kbyte 32kbyte mb9af115napmc - g - jne2 384kbyte 32kbyte mb9af116napmc - g - jne2 512kbyte 32kbyte mb9af111napf - g - jne1 64kbyte 16kbyte plastic ? qfp (0.65mm pitch), 100 - pin ( fpt - 100p - m06) mb9af112napf - g - jne1 128kbyte 16kbyte mb9af114napf - g - jne1 256kbyte 32kbyte mb9af115napf - g - jne1 384kbyte 32kbyte mb9af116napf - g - jne1 512kbyte 32kbyte mb9af111nabgl - ge1 64kbyte 16kbyte plastic ? pfbga (0.8mm pitch), 112 - pin (bga - 112p - m04) mb9af112nabgl - ge1 128kbyte 16kbyte mb9af114nabgl - ge1 256kbyte 32kbyte d a t a s h e e t 106 mb9a110a - ds706 - 00011 - 3v0 - e, december 1 6 , 2014 confidential ? package dimensions 100-pin plastic lqfp lead pitch 0.50 mm pa ck age width pa ck age length 14.00 mm 14.00 mm lead shape gullwing lead bend direction no rm al bend sealing method plastic mold mounting height 1.70 mm max we ight 0.65 g 100-pin plastic lqfp (fpt-100p-m23) (fpt-100p-m23) c 2009-2010 fujitsu semiconductor limited f100034s-c-3-4 16.000.20(.630.008)sq 1 25 51 76 75 100 0.50(.020) 0.220.05 m 0.08(.003) *14.000.10(.551.004)sq 26 50 0.1450.055 (.006.002) 0.08(.003) "a" index 0 ~8 0.500.20 0.100.10 (stand off) + .008 + 0.20 (mounting height) - 0.10 1.50 .059 - .004 ( ) 0.600.15 0.25(.010) dimensions in mm (inches). note:the values in parentheses are reference values. note 1) * : these dimensions do not include resin protrusion. note 2) pins width and pins thickness include plating thickness. note 3) pins width do not include tie bar cutting remainder. details of "a" part (.004.004) (.009.002) (.020.008) (.024.006) d a t a s h e e t december 1 6 , 2014 , mb9a110a - ds706 - 00011 - 3v0 - e 107 confidential 100-pin plastic qf p l ead pitch 0.65 mm pa ck age width pa ck age length 14.00 20.00 mm lead shape gullwing sealing method plastic mold mounting height 3.35 mm ma x code (reference ) p-qfp100-14 20-0.65 100-pin plastic qf p (fpt -100p-m06) (fpt-100p-m06) c 2002-2010 fujitsu semiconductor limited f100008s-c-5-7 1 30 31 50 51 80 81 100 20.000.20(.787.008) 23.900.40(.941.016) (.551.008) 17.900.40 (.705.016) index 0.65(.026) 0.320.05 (.013.002) m 0.13(.005) "a" 0.170.06 (.007.002) 0.10(.004) details of "a" part (.035.006) 0.880.15 (.031.008) 0.800.20 0.25(.010) 3.00 +0.35 C0.20 +.014 C.008 .118 (mounting height) 0.250.20 (.010.008) (stand off) 0~8 * * 14.000.20 dimensions in mm (inches). note: the values in parentheses are reference values. note 1) * : these dimensions do not include resin protrusion. note 2) pins width and pins thickness include plating thickness. note 3) pins width do not include tie bar cutting remainder. d a t a s h e e t 108 mb9a110a - ds706 - 00011 - 3v0 - e, december 1 6 , 2014 confidential 80-pin plastic lqfp lead pitch 0.50 mm pa ck age width pa ck age length 12.00 mm 12.00 mm lead shape gullwing lead bend direction no rm al bend sealing method plastic mold mounting height 1.70 mm max we ight 0.47 g 80-pin plastic lqfp (fpt-80p-m37) (fpt-80p-m37) 2009-2010 fujitsu semiconductor limited f80037s-c-1-2 1 20 40 21 60 41 80 61 index *12.00 0.10(.472 .004)sq 14.00 0.20(.551 .008)sq 0.50(.020) 0.22 0.05 (.009 .002) m 0.08(.003) 0.145 0.055 (.006 .002) 0.08(.003) "a" (stand off) details of "a" part (.004 .002) 0.10 0.05 (.024 .006) 0.60 0.15 (.020 .008) 0.25(.010) 0.50 0.20 (mounting height) .059 C .004 +.008 C 0.10 +0.20 1.50 0~8 c dimensions in mm (inches). note: the values in parentheses are reference values. note 1) * : these dimensions do not include resin protrusion. note 2) pins width and pins thickness include plating thickness. note 3) pins width do not include tie bar cutting remainder. d a t a s h e e t december 1 6 , 2014 , mb9a110a - ds706 - 00011 - 3v0 - e 109 confidential 64-pin plastic lqfp lead pitch 0.50 mm pa ck age width pa ck age length 10.00 mm 10.00 mm lead shape gullwing lead bend direction no rm al bend sealing method plastic mold mounting height 1.70 mm max we ight 0.32 g 64-pin plastic lqfp (fpt-64p-m38) (fpt-64p-m38) "a" 0.08(.003) 0.145 0.055 (.006 .002) 0.08(.003) m 0.220.05 0.50(.020) 12.000.20(.472.008)sq *10.000.10(.394.004)sq index 49 64 33 48 17 32 16 1 2010 fujitsu semiconductor limited f64038s-c-1-2 (stand off) details of "a" part 0.10 0.10 (.004.004) 0.60 0.15 0.25(.010) c 0.500.20 (.020.008) (mounting height) .059 C .004 +.00 8 C 0.10 +0.20 1.50 0~8 dimensions in mm (inches). note: the values in parentheses are reference values. note 1) * : these dimensions do not include resin protrusion. note 2) pins width and pins thickness include plating thickness. note 3) pins width do not include tie bar cutting remainder. (.009.002) (.024.006) d a t a s h e e t 110 mb9a110a - ds706 - 00011 - 3v0 - e, december 1 6 , 2014 confidential 64-pin plastic lqfp lead pitch 0.65 mm pa ck age width pa ck age length 12.00 mm 12.00 mm lead shape gullwing sealing method plastic mold mounting height 1.70 mm max we ight 0.47 g 64-pin plastic lqfp (fpt -64p-m39) (fpt-64p-m39) "a" 0.10(.004) 0.1450.055 (.006.002) 0.13(.005) m 0.320.05 0.65(.026) 14.000.20(.551.008)sq 12.000.10(.472.004)sq index 49 64 33 48 17 32 16 1 2010-2011 fujitsu semiconductor limited hmbf64-39sc-2-2 details of "a" part 0.100.10 0.600.15 (.024.006) 0.25(.010)bsc c .059 C .004 +.008 C 0.10 +0.20 1.50 0~8? 0.500.20 di mensions in mm (inches). no te: the values in parentheses are reference values. note 1) pins width and pins thickness include plating thickness. (.013.002) (.020.008) (.004.004) d a t a s h e e t december 1 6 , 2014 , mb9a110a - ds706 - 00011 - 3v0 - e 111 confidential 112-ball plastic pfbga ball pitch 0.80 mm pa ck age width pa ck age length 10.00 10.00 mm lead shape soldering ball sealing method plastic mold ball si ze 0.45 mm mounting height 1.45 mm max. we ight 0.22 g 112-ball plastic pfbg a (bga-112p-m04 ) (bga-112p-m04) c 2003-2010 fujitsu semiconductor limited b112004s-c-2-3 10.000.10(.394.004) (.049.008) 1.250.20 (seated height) 6 f index (index area) 10.000.10 (.394.004) (112-0.18.004) 112-0.45010 0.350.10 (.014.004) (stand off) 0.10(.004) s b a g h j k le dc ba 7 8 9 10 11 5 4 3 2 1 0.80(.031) ref ref 0.80(.031) 0.08(.003) b a s m 0.20(.008) sb s a s 0.20(.008) dimensions in mm (inches). note: the values in parentheses are reference values. d a t a s h e e t 112 mb9a110a - ds706 - 00011 - 3v0 - e, december 1 6 , 2014 confidential 64-pin plastic qfn lead pitch 0.50 mm package width package length 9.00 mm 9.00 mm sealing method plastic mold mounting height 0.90 mm max weight - 64-pin plastic qf n (lcc-64p-m24) (lcc-64p-m24) c 2011 fujitsu semiconductor limited hmbc64-24sc-2-1 (.354.004) 9.000.10 (.236.004) 6.000.10 (.236.004) 6.000.10 (.354.004) 9.000.10 0.400.05 (.016.002) 0.50 (.020) (typ) 0.250.05 (.010.002) 0.45 (.018) 1pin id (0.20r (.008r)) 0.05 (.002) max (0.20 (.008)) 0.850.05 (.033.002) index area dimensions in mm (inches). note: the values in parentheses are reference values. d a t a s h e e t december 1 6 , 2 014 , mb9a110a - ds706 - 00011 - 3v0 - e 113 confidential ? major changes page section change results revision 1.0 - - initial release revision 2.0 - - ? revised series name and part number: mb9a110 series mb9a110 a series mb9af111l MB9AF111LA mb9af112l mb9af112la mb9af114l mb9af114la mb9af111m mb9 af111ma mb9af112m mb9af112ma mb9af114m mb9af114ma mb9af115m mb9af115ma mb9af116m mb9af116ma mb9af111n mb9af111na mb9af112n mb9af112na mb9af114n mb9af114na mb9af115n mb9af115na mb9af116n mb9af116na ? added the package. lcc - 64p - m2 4 8 ? product lineup ? ? function multi - function serial interface (uart/csio/lin/i 2 c) added the following description. ch.4 to ch.7: fifo (16steps 9 - bit) ch.0 to ch.3: no fifo ? external interrupts corrected the following description. 7pins (max) 8p ins (max) 34 to 37 ? signal description multi - function serial (ch.0 to ch.7) corrected the description for function. ? added "lin pin" ? deleted "uart pin" 42, 43 ? i/o circuit type ? corrected the following s chematic for " typeb " . cmos level hysteresis in put digital input ? corrected the following s chematic for " typec " . control pin digital output 51 ? handling device s ? power supply pins corrected the description. 54 ? memory size ? added " ? memory size " . 69 ? electrical characteristics 4. ac characteri stics (1) main clock i nput characteristics added the items f cm to the i nternal operating clock frequency. 71 (4 - 2) operating conditions of main pll ? added the description. 72 ( 7 ) external bus timing ? external bus clock out put characteristics ? 79 ( 8 ) b ase timer input timing ? trigger input timing ? added the note. 88 ( 10 ) external input timing ? corrected the footnote. 94 6. 12 - bit a/d converter ? electrical characteristics for the a/d converter ? ? corrected the value of " full - scale transition voltage ". min: - 20 avrh - 20 max: +20 avrh+20 ? corrected the value of "compare clock cycle". max: 10000 2000 ? corrected the value of "reference voltage ". min: avss 2.7 revision 2.1 - - company name and layout design change revision 3.0 3 ? features ? external bus interface ? added the description of maximum area size 9 ? packages ? deleted fpt - 64p - m24, fpt - 64p - m23, fpt - 80p - m21, fpt - 100p - m20 44, 46 ? i/o circuit type ? added the description of i 2 c to the type of e, f and i 44, 45 ? i/o circuit type ? added abou t +b input 51 ? handling devices ? added " ? s tabilizing power supply voltage" d a t a s h e e t 114 mb9a110a - ds706 - 00011 - 3v0 - e, december 1 6 , 2014 confidential page section change results 51 ? handling devices ? c rystal oscillator circuit ? added the following description "evaluate oscillation of your using crystal oscillator by your mount board." 52 ? handling devices ? c pin ? changed the description 53 ? block diagram ? modified the block diagram 54 ? memory size ? changed to the following description see " ? memory size" in " ? product lineup" to confirm the memory size. 55 ? memory map memory map(1) ? modified the area of "ext arnal device area" 56, 57 ? memory map memory map(2) (3) ? added the summary of flash memory sector and the note 64 , 65 ? electrical characteristics 1. absolute maximum ratings ? added the clamp maximum current added the output current of p80 and p81 ad ded about +b input 66 ? electrical characteristics 2. recommended operation conditions ? modified the minimum value of analog reference voltage added smoothing capacitor added the note about less than the minimum power supply voltage 67, 68 ? electrica l characteristics 3. dc characteristics (1) current rating ? changed the table format added main timer mode current added flash memory current moved a/d converter current 71 ? electrical characteristics 4. ac characteristics (3) built - in cr oscillati on characteristics ? added frequency stability time at built - in high - speed cr 72 ? electrical characteristics 4. ac characteristics (4 - 1) (4 - 2) operating conditions of main pll ? added main pll clock frequency added the figure of main pll connection 73 ? el ectrical characteristics 4. ac characteristics (6) power - on reset timing ? added time until releasing power - on reset changed the figure of timing 75 - 77 ? electrical characteristics 4. ac characteristics (7) external bus timing ? modified data output time 82 - 89 ? electrical characteristics 4. ac characteristics ( 8 ) csio/uart timing ? modified from uart timing to csio/uart timing changed from internal shift clock operation to master mode changed from external shift clock operation to slave mode 96 ? elect rical characteristics 5. 12bit a/d converter ? added the typical value of integral nonlinearity, differential nonlinearity, zero transition voltage and full - scale transition voltage modified stage transition time to operation permission modified the mi nimum value of reference voltage 101 ? electrical characteristics 9. return time from low - power consumption mode ? added return time from low - power consumption mode 105 ? ordering information ? change to full part number 106 ? package dimensions ? deleted fpt - 64 p - m24, fpt - 64p - m23, fpt - 80p - m21, fpt - 100p - m20 d a t a s h e e t december 1 6 , 2 014 , mb9a110a - ds706 - 00011 - 3v0 - e 115 confidential d a t a s h e e t 116 mb9a110a - ds706 - 00011 - 3v0 - e, december 1 6 , 2014 confidential d a t a s h e e t december 1 6 , 2 014 , mb9a110a - ds706 - 00011 - 3v0 - e 117 confidential d a t a s h e e t 118 mb9a110a - ds706 - 00011 - 3v0 - e, december 1 6 , 2014 confidential colophon the products described in this document are designed, developed and manufactured as contemplated for general use, including without limitat ion, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for any use that includes fatal risks or dangers that, unless extremely high safety is secured, could ha ve a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffi c control, mass transport control, medical li fe support system, missile launch control in weapon system), or (2) for any use where chance of failure is intolerable (i.e., submersible repeater and artificial satellite). please note that spansion will not be liable to you and/or any third party for any claims or damages arising in connection with above - mentioned uses of the products. any semiconductor devices have an inherent chance of failure. you must protect against injury, damage or loss from such failures by incorporating safety design measures int o your facility and equipment such as redundancy, fire protection, and prevention of over - current levels and other abnormal operating conditions. if any products described in this document represent goods or technologies subject to certain restrictions on export under the foreign exchange and foreign trade law of japan, the us export administration regulations or the applicable laws of any other country, the prior authorization by the respective government entity will be required for export of those product s. trademarks and notice the contents of this document are subject to change without notice. this document may contain information on a spansion product under development by spansion. spansion reserves the right to change or discontinue work on any produc t without notice. the information in this document is provided as is without warranty or guarantee of any kind as to its accuracy, completeness, operability, fitness for particular purpose, merchantability, non - infringement of third - party rights, or any ot her warranty, express, implied, or statutory. spansion assumes no liability for any damages of any kind arising out of the use of the information in this document. copyright ? 2011 - 201 4 spansion all rights reserved. spansion ? , the spansion logo, mir rorbit ? , mirrorbit ? eclipse tm , ornand tm , easy designsim tm , traveo tm and combinations thereof, are trademarks and registered trademarks of spansion llc in the united states and other countries. other names used are for informational purposes only and may b e trademarks of their respective owners. |
Price & Availability of MB9AF111LA
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |